Hi Alex,

> From: Alex Williamson <alex.william...@redhat.com>
> Sent: Saturday, September 12, 2020 6:13 AM
> 
> On Thu, 10 Sep 2020 03:45:30 -0700
> Liu Yi L <yi.l....@intel.com> wrote:
> 
> > This patch exposes PCIe PASID capability to guest for assigned devices.
> > Existing vfio_pci driver hides it from guest by setting the capability
> > length as 0 in pci_ext_cap_length[].
> 
> This exposes the PASID capability, but it's still read-only, so this largely 
> just helps
> userspace know where to emulate the capability, right?  Thanks,

oh, yes. This path only makes it visible to userspace. perhaps, I should
refine the commit message and the patch name. right?

Regards,
Yi Liu

> Alex
> 
> > And this patch only exposes PASID capability for devices which has
> > PCIe PASID extended struture in its configuration space. VFs will not
> > expose the PASID capability as they do not implement the PASID
> > extended structure in their config space. It is a TODO in future.
> > Related discussion can be found in below link:
> >
> > https://lore.kernel.org/kvm/20200407095801.648b1...@w520.home/
> >
> > Cc: Kevin Tian <kevin.t...@intel.com>
> > CC: Jacob Pan <jacob.jun....@linux.intel.com>
> > Cc: Alex Williamson <alex.william...@redhat.com>
> > Cc: Eric Auger <eric.au...@redhat.com>
> > Cc: Jean-Philippe Brucker <jean-phili...@linaro.org>
> > Cc: Joerg Roedel <j...@8bytes.org>
> > Cc: Lu Baolu <baolu...@linux.intel.com>
> > Signed-off-by: Liu Yi L <yi.l....@intel.com>
> > Reviewed-by: Eric Auger <eric.au...@redhat.com>
> > ---
> > v5 -> v6:
> > *) add review-by from Eric Auger.
> >
> > v1 -> v2:
> > *) added in v2, but it was sent in a separate patchseries before
> > ---
> >  drivers/vfio/pci/vfio_pci_config.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/vfio/pci/vfio_pci_config.c
> > b/drivers/vfio/pci/vfio_pci_config.c
> > index d98843f..07ff2e6 100644
> > --- a/drivers/vfio/pci/vfio_pci_config.c
> > +++ b/drivers/vfio/pci/vfio_pci_config.c
> > @@ -95,7 +95,7 @@ static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX +
> 1] = {
> >     [PCI_EXT_CAP_ID_LTR]    =       PCI_EXT_CAP_LTR_SIZEOF,
> >     [PCI_EXT_CAP_ID_SECPCI] =       0,      /* not yet */
> >     [PCI_EXT_CAP_ID_PMUX]   =       0,      /* not yet */
> > -   [PCI_EXT_CAP_ID_PASID]  =       0,      /* not yet */
> > +   [PCI_EXT_CAP_ID_PASID]  =       PCI_EXT_CAP_PASID_SIZEOF,
> >  };
> >
> >  /*

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