On 2021-03-18 09:55, chenxiang (M) wrote:
Hi will,
在 2021/3/18 17:34, Will Deacon 写道:
On Thu, Mar 18, 2021 at 11:21:24AM +0800, chenxiang wrote:
From: Xiang Chen <chenxian...@hisilicon.com>
Fix a type "SAC" to "DAC" in the comment of function
iommu_dma_alloc_iova().
Signed-off-by: Xiang Chen <chenxian...@hisilicon.com>
---
drivers/iommu/dma-iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index af765c8..3bc17ee 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -443,7 +443,7 @@ static dma_addr_t iommu_dma_alloc_iova(struct
iommu_domain *domain,
if (domain->geometry.force_aperture)
dma_limit = min(dma_limit,
(u64)domain->geometry.aperture_end);
- /* Try to get PCI devices a SAC address */
+ /* Try to get PCI devices a DAC address */
if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev))
iova = alloc_iova_fast(iovad, iova_len,
DMA_BIT_MASK(32) >> shift, false);
This doesn't look like a typo to me... Please explain.
As the author of said comment, it is definitely not a typo.
I think it means double-address cycle(DAC), and in LLD3 452 page, there
is a description about it "PCI double-address cycle mappings Normally,
the DMA support layer works with 32-bit bus addresses, possibly
restricted by a specific device’s DMA mask. The PCI bus, however, also
supports a 64-bit addressing mode, the double-address cycle (DAC)."
Please point it out if i am wrong :)
Yes, now look at what the code above does: *if* a PCI device has a DMA
mask greater than 32 bits (i.e. can support dual address cycles), we
first try an IOVA allocation with an explicit 32-bit limit (i.e. that
can be expressed in a single address cycle), in the hope that we don't
have to fall back to allocating from the upper range and forcing the
device to actually use DAC (and suffer the potential performance impact).
Robin.
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