Well, the  need to reduce silicon real estate is very noble
indeed. The price and density of silicon goes down by a factor
of 2 every 2 years so, and the flow-label legacy would probably
last beyond that. So the pertinent question to answer would be
how do we assign the bits in a way that they would still be
useful 10 years from now.

Subrata


-----Original Message-----
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED]]On Behalf Of Michael Thomas
Sent: Wednesday, December 26, 2001 4:29 PM
To: Perry E. Metzger
Cc: Michael Thomas; [EMAIL PROTECTED]
Subject: Re: Flow Label


Perry E. Metzger writes:
 > Michael Thomas <[EMAIL PROTECTED]> writes:
 > > Perry E. Metzger writes:
 > >  > I'm looking for statements from several router vendors that look
much
 > >  > like this:
 > >
 > >    I don't speak for Cisco. I speak for myself.
 > >
 > >    Sorry.
 >
 > Well, speaking for yourself, can you describe your simulations of
 > hardware performance with and without the flow label?

   I'm not especially interested in this game
   because some hardware geek somewhere is
   bound to throw enough transistors at the
   problem and claim that it doable. Big deal.
   It's an empty claim because it doesn't say
   what was given up in the process. I have
   witnessed firsthand hardware engineers on
   high end platforms react somewhere between
   disbelief and outright hostility at the
   prospect of chasing down header chains at
   line rate. CAM's -- as I've mention three
   times now -- are especially sensitive to
   bone headed standards potato blunders of
   this kind; I forget, but the transistor
   count is O(n^2) or maybe worse with the
   number of bits needed to form the key. IP6
   is already at a big disadvantage given the
   need to key off of ~256 bits vs. 64 bits
   just for addresses. And lest you think
   that I'm just concerned about CAM based forwarding
   planes, think again; they all need to view
   enough of the header to classify, and that
   always impacts silicon as it gets bigger.
   Thus you get these choices: pay more than you
   should have, get worse performance, or delete
   other features you might have liked to go
   faster on a finite transistor budget.

   Oh, and you might ask your hardware vendors
   who claim to do this whether they can deal
   with flow classification of mobile IP with
   route optimization at line rate. And since
   MIPv6 route optimization is about as stable as
   jello, will they have the resilience to change
   their flow classier if it changes too?

              Mike
--------------------------------------------------------------------
IETF IPng Working Group Mailing List
IPng Home Page:                      http://playground.sun.com/ipng
FTP archive:                      ftp://playground.sun.com/pub/ipng
Direct all administrative requests to [EMAIL PROTECTED]
--------------------------------------------------------------------

--------------------------------------------------------------------
IETF IPng Working Group Mailing List
IPng Home Page:                      http://playground.sun.com/ipng
FTP archive:                      ftp://playground.sun.com/pub/ipng
Direct all administrative requests to [EMAIL PROTECTED]
--------------------------------------------------------------------

Reply via email to