On Tue, 2008-04-29 at 20:27 -0400, Ryan Watts wrote:
> Andy,
> 
> How am I to apply this patch?  I tried 'patch -p0 <
> cx18-i2c-debugging.patch' after extracting the tip.tar.bz2.


$ cd v4l-dvb-9377f0ecba44
$ patch -p1 < ../cx18-i2c-debugging.patch

The '-p1' will cause patch to discard up to and including the first "/"
in the file names: the "a/" and "b/" in this case.

>   I noticed some things in the patch file:
> 
> Line 1: "diff -r 9377f0ecba44
> linux/drivers/media/video/cx18/cx18-driver.c"
> 
> My directory is named "v4l-dvb-9377f0ecba44". Is this correct?  I
> tried changing it, but that didn't work.
> 
> Also,
> Line 2: "--- a/linux/drivers/media/video/cx18/cx18-driver.c Mon Apr 28
> 22:27:08 2008 +0200"
> Line 3: "+++ b/linux/drivers/media/video/cx18/cx18-driver.c Mon Apr 28
> 21:32:05 2008 -0400"
> 
> What are the "a" and "b" directories?

I made the patch using the hg (mercurial) revision control client
instead of a diff from the tar archive.  The "a" and "b" are something
that hg just does.  Sorry for any confusion.


Ryan,

Found the datasheet for the VIA VT8363A Northbridge chip that includes
the Host bridge and AGP bridge devices.  Your Northbridge is either this
one or a variant without the A.

Go here:
http://www.datasheet4u.com/html/V/T/8/VT8363A_VIA.pdf.html
and click on the "Datasheet view" link, if you want a copy.

>From your lspci output:


> 00:00.0 Host bridge [0600]: VIA Technologies, Inc. VT8363/8365 [KT133/KM133] 
> [1106:0305] (rev 03)
>       Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
> Stepping- SERR- FastB2B-
>       Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
> <TAbort- <MAbort+ >SERR- <PERR-
>       Latency: 8
>       Region 0: Memory at d8000000 (32-bit, prefetchable) [size=64M]
>       Capabilities: <access denied>
> 00: 06 11 05 03 06 00 10 22 03 00 00 06 00 08 00 00
                           ^
                           |
                           |
At least 1 transaction had been aborted by a master on the PCI bus,
since the machine was started.

The (CPU) host bridge is also only allowed a latency of 8 bus cycles. 
This means that the CPU can only transfer a maximum of (8-2)*4 = 24
bytes or so, before it has to give up the PCI bus and then try to grab
it again.

(My host bridge in my machine has a value of 64 set for latency.)


> 10: 08 00 00 d8 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
> 
> 00:01.0 PCI bridge [0604]: VIA Technologies, Inc. VT8363/8365 [KT133/KM133 
> AGP] [1106:8305] (prog-if 00 [Normal decode])
>       Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
> Stepping- SERR- FastB2B-
>       Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
> <TAbort- <MAbort+ >SERR- <PERR-
>       Latency: 0
>       Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
>       I/O behind bridge: 0000f000-00000fff
>       Memory behind bridge: e1000000-e2ffffff
>       Prefetchable memory behind bridge: d0000000-d7ffffff
>       Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
> <MAbort- <SERR- <PERR-
>       BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B-
>       Capabilities: <access denied>
> 00: 06 11 05 83 07 00 30 22 00 00 04 06 00 00 01 00
                           ^
                           |
The AGP bridge had also noted that at least 1 transaction had been
aborted by a master on the PCI bus, since the machine was started.

> 10: 00 00 00 00 00 00 00 00 00 01 01 00 f0 00 00 00
> 20: 00 e1 f0 e2 00 d0 f0 d7 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 0c 00


I'm suspect, some of CX23418 problems are related to PCI errors or
aborts.

I'd like to fix the cx18 driver to work well in the face of such errors.
There is at least one potential problem in cx18_setscl() and
cx18_setsda(): they use a read, modify, write strategy to change the
CX23418's registers.  If we get a bogus 0xffffffff (or something else)
back from a bad read on the PCI bus, we trash the register.

My logs with the patch and debug turned on looked like this:
Apr 28 21:03:15 palomino kernel: cx18:  Start initialization, version 1.0.0
Apr 28 21:03:15 palomino kernel: cx18-0: Initializing card #0
Apr 28 21:03:15 palomino kernel: cx18-0: Autodetected Hauppauge card
Apr 28 21:03:15 palomino kernel: ACPI: PCI Interrupt 0000:02:01.0[A] -> GSI 21 
(level, low) -> IRQ 21
Apr 28 21:03:15 palomino kernel: cx18-0: cx23418 revision 01010000 (B)
Apr 28 21:03:15 palomino kernel: cx18-0 i2c: i2c init
Apr 28 21:03:15 palomino kernel: cx180 i2c: cx18_setscl: On entry 
CX18_REG_I2C_1_WR = 0x21c0b
Apr 28 21:03:15 palomino kernel: cx180 i2c: cx18_setscl: Wrote    
CX18_REG_I2C_1_WR = 0x21c0b
Apr 28 21:03:15 palomino kernel: cx180 i2c: cx18_setscl: Readback 
CX18_REG_I2C_1_WR = 0x21c0b
Apr 28 21:03:15 palomino kernel: cx180 i2c: cx18_setsda: On entry 
CX18_REG_I2C_1_WR = 0x21c0b
Apr 28 21:03:15 palomino kernel: cx180 i2c: cx18_setsda: Wrote    
CX18_REG_I2C_1_WR = 0x21c0b
Apr 28 21:03:15 palomino kernel: cx180 i2c: cx18_setsda: Readback 
CX18_REG_I2C_1_WR = 0x21c0b
Apr 28 21:03:15 palomino kernel: cx180 i2c: cx18_setscl: On entry 
CX18_REG_I2C_2_WR = 0x21c0b
Apr 28 21:03:15 palomino kernel: cx180 i2c: cx18_setscl: Wrote    
CX18_REG_I2C_2_WR = 0x21c0b
Apr 28 21:03:15 palomino kernel: cx180 i2c: cx18_setscl: Readback 
CX18_REG_I2C_2_WR = 0x21c0b


Regards,
Andy


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