This was not respected on ARM before. Nevertheless, assume 32 bit MMIO
access width as default.

Signed-off-by: Ralf Ramsauer <[email protected]>
---
 inmates/lib/arm-common/include/uart.h |  3 +++
 inmates/lib/arm/printk.c              | 21 +++++++++++++++++++++
 inmates/lib/arm/uart-8250.c           | 19 +++++++++----------
 inmates/lib/arm/uart-pl011.c          | 14 +++++++-------
 4 files changed, 40 insertions(+), 17 deletions(-)

diff --git a/inmates/lib/arm-common/include/uart.h 
b/inmates/lib/arm-common/include/uart.h
index 8bd9c77529e1..0142b3112743 100644
--- a/inmates/lib/arm-common/include/uart.h
+++ b/inmates/lib/arm-common/include/uart.h
@@ -21,4 +21,7 @@ struct uart_chip {
        void (*init)(struct uart_chip*);
        void (*wait)(struct uart_chip*);
        void (*write)(struct uart_chip*, char c);
+
+       void (*reg_out)(void*, u32);
+       u32 (*reg_in)(void*);
 };
diff --git a/inmates/lib/arm/printk.c b/inmates/lib/arm/printk.c
index c286cf5974de..4d0497b22791 100644
--- a/inmates/lib/arm/printk.c
+++ b/inmates/lib/arm/printk.c
@@ -39,6 +39,17 @@ static struct uart_chip *chip = NULL;
 
 extern struct uart_chip uart_8250_ops, uart_pl011_ops;
 
+
+static void mmio8_out(void *address, u32 value)
+{
+       mmio_write8(address, (u8)value);
+}
+
+static u32 mmio8_in(void *address)
+{
+       return mmio_read8(address);
+}
+
 static void console_write(const char *msg)
 {
        char c = 0;
@@ -71,6 +82,16 @@ static void dbg_init(void)
        if (!chip)
                return;
 
+       /* Assume 32-bit MMIO width by default */
+       chip->reg_out = mmio_write32;
+       chip->reg_in = mmio_read32;
+
+       width = cmdline_parse_int("dbg-width", 32);
+       if (width == 8) {
+               chip->reg_out = mmio8_out;
+               chip->reg_in = mmio8_in;
+       }
+
        chip->base = (void *)(unsigned long)
                cmdline_parse_int("dbg-base", DBG_BASE);
        chip->divider = cmdline_parse_int("dbg-divider", DBG_DIVIDER);
diff --git a/inmates/lib/arm/uart-8250.c b/inmates/lib/arm/uart-8250.c
index aee8cb991489..792913845804 100644
--- a/inmates/lib/arm/uart-8250.c
+++ b/inmates/lib/arm/uart-8250.c
@@ -12,7 +12,6 @@
  * the COPYING file in the top-level directory.
  */
 
-#include <jailhouse/mmio.h>
 #include <jailhouse/processor.h>
 #include <uart.h>
 
@@ -28,27 +27,27 @@
 static void uart_init(struct uart_chip *chip)
 {
        if (chip->clock_reg)
-               mmio_write32(chip->clock_reg,
-                            mmio_read32(chip->clock_reg) |
-                            (1 << chip->gate_nr));
+               chip->reg_out(chip->clock_reg,
+                             chip->reg_in(chip->clock_reg) |
+                             (1 << chip->gate_nr));
 
        if (chip->divider) {
-               mmio_write32(chip->base + UART_LCR, UART_LCR_DLAB);
-               mmio_write32(chip->base + UART_DLL, chip->divider);
-               mmio_write32(chip->base + UART_DLM, 0);
-               mmio_write32(chip->base + UART_LCR, UART_LCR_8N1);
+               chip->reg_out(chip->base + UART_LCR, UART_LCR_DLAB);
+               chip->reg_out(chip->base + UART_DLL, chip->divider);
+               chip->reg_out(chip->base + UART_DLM, 0);
+               chip->reg_out(chip->base + UART_LCR, UART_LCR_8N1);
        }
 }
 
 static void uart_wait(struct uart_chip *chip)
 {
-       while (!(mmio_read32(chip->base + UART_LSR) & UART_LSR_THRE))
+       while (!(chip->reg_in(chip->base + UART_LSR) & UART_LSR_THRE))
                cpu_relax();
 }
 
 static void uart_write(struct uart_chip *chip, char c)
 {
-       mmio_write32(chip->base + UART_TX, c);
+       chip->reg_out(chip->base + UART_TX, c);
 }
 
 struct uart_chip uart_8250_ops = {
diff --git a/inmates/lib/arm/uart-pl011.c b/inmates/lib/arm/uart-pl011.c
index a3d88af3e672..79f404eaa0d3 100644
--- a/inmates/lib/arm/uart-pl011.c
+++ b/inmates/lib/arm/uart-pl011.c
@@ -41,13 +41,13 @@ static void uart_init(struct uart_chip *chip)
        u32 bauddiv = UART_CLK / (16 * 115200);
        void *base = chip->virt_base;
 
-       mmio_write16(base + UARTCR, 0);
-       while (mmio_read8(base + UARTFR) & UARTFR_BUSY)
+       chip->reg_out(base + UARTCR, 0);
+       while (chip->reg_in(base + UARTFR) & UARTFR_BUSY)
                cpu_relax();
 
-       mmio_write8(base + UARTLCR_H, UARTLCR_H_WLEN);
-       mmio_write16(base + UARTIBRD, bauddiv);
-       mmio_write16(base + UARTCR, (UARTCR_EN | UARTCR_TXE | UARTCR_RXE |
+       chip->reg_out(base + UARTLCR_H, UARTLCR_H_WLEN);
+       chip->reg_out(base + UARTIBRD, bauddiv);
+       chip->reg_out(base + UARTCR, (UARTCR_EN | UARTCR_TXE | UARTCR_RXE |
                                     UARTCR_Out1 | UARTCR_Out2));
 #endif
 }
@@ -57,14 +57,14 @@ static void uart_wait(struct uart_chip *chip)
        u32 flags;
 
        do {
-               flags = mmio_read32(chip->virt_base + UARTFR);
+               flags = chip->reg_in(chip->virt_base + UARTFR);
                cpu_relax();
        } while (flags & (UARTFR_TXFF | UARTFR_BUSY)); /* FIFO full or busy */
 }
 
 static void uart_write(struct uart_chip *chip, char c)
 {
-       mmio_write32(chip->virt_base + UARTDR, c);
+       chip->reg_out(chip->virt_base + UARTDR, c);
 }
 
 struct uart_chip uart_pl011_ops = {
-- 
2.10.2

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