We do have those accessors, so use them. Eliminated all m{rc,cr}'s.
Signed-off-by: Ralf Ramsauer <[email protected]>
---
hypervisor/arch/arm/caches.S | 2 +-
inmates/lib/arm/header.S | 5 ++++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/hypervisor/arch/arm/caches.S b/hypervisor/arch/arm/caches.S
index 2bff5212b9..44b1fa3aec 100644
--- a/hypervisor/arch/arm/caches.S
+++ b/hypervisor/arch/arm/caches.S
@@ -54,7 +54,7 @@ loop_ways:
orr r10, r9, r8, lsl r5 @ Factor in the way and cache numbers
orr r10, r10, r7, lsl r2 @ Factor in the index number
- mcr p15, 0, r10, c7, c10, 2 @ DCCSW
+ arm_write_sysreg(DCCSW, r10)
subs r7, r7, #1 @ decrement index
bge loop_ways
diff --git a/inmates/lib/arm/header.S b/inmates/lib/arm/header.S
index 3c2f3d6ae4..72fe3a0602 100644
--- a/inmates/lib/arm/header.S
+++ b/inmates/lib/arm/header.S
@@ -11,6 +11,9 @@
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*/
+
+#include <asm/sysregs.h>
+
.arm
.section ".boot", "ax"
@@ -41,7 +44,7 @@ vectors:
.globl __reset_entry
__reset_entry:
ldr r0, =vectors
- mcr p15, 0, r0, c12, c0, 0 @ VBAR
+ arm_write_sysreg(VBAR, r0)
mov r0, #0
ldr r1, =bss_start
--
2.12.0
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