On Mon, Oct 30, 2017 at 12:32:19PM +0100, Jan Kiszka wrote: >On 2017-10-30 11:07, Peng Fan wrote: >>>>>> Is Big.Little(A53+A72) supported? >>>>> >>>>> I didn't try, but I expect it work as long as all cores are exposed as >>>>> if they were equal. >>>> >>>> In my case A53 is the first cluster, A72 is in the second cluster. A72 runs >>>> faster that A53, so when enabling jailhouse, A72 will first finish >>>> initializing jailhouse. >>> >>> Who is managing the cluster switch, Linux or something in firmware? In >>> order to let Jailhouse do its work properly, all cores need to be >>> enabled by it during setup, not just one cluster. IOW, all cores need to >>> be seen by Linux as individual cores. >> >> firmware handles cluster. >> In my case it is >> CPU 4 ... OK (A72) >> CPU 5 ... OK (A72) >> CPU 2 ... OK (A53) >> CPU 3 ... OK (A53) >> CPU 0 ... OK (A53) >> CPU 1 ... OK (A53) >> >> .... >> >> When A53 backing to Linux side, A53 reports parking CPU. Jtag shows stage1 - >> stage 2 >> MMU table corrupt. > >What is the exact error report along "Parking CPU ..."?
#~/jailhouse# ./jailhouse enable imx8.cell Initializing Jailhouse hypervisor v0.7 (115-g5f7d20ca-dirty) on CPU 5 Code location: 0x0000ffffc0200060 Page pool usage after early setup: mem 37/997, remap 96/131072 Initializing processors: CPU 5... OK CPU 4... OK CPU 2... OK CPU 0... OK CPU 1... OK CPU 3... OK Page pool usage after late setup: mem 40/997, remap 368/131072 FATAL: instruction abort at 0x8156ce6c FATAL: forbidden access (exception class 0x20) Cell state before exception: pc: ffff000000bd0e6c lr: ffff000000bd0e6c spsr: 600001c5 EL1 sp: ffff8008fff33fb0 esr: 20 1 0000084 x0: 0000000000000000 x1: 0000000000000000 x2: 0000000000000000 x3: 0000000000000000 x4: 0000000000000000 x5: 0000000000000000 x6: 0000000000000000 x7: 0000000000000000 x8: 0000000000000000 x9: 0000000000000000 x10: 0000000000000000 x11: 0000000000000000 x12: 0000000000000000 x13: 0000000000000000 x14: 0000000000000000 x15: 0000000000000000 x16: 0000000000000000 x17: 0000000000000000 x18: 0000000000000000 x19: ffff000000bd4910 x20: 0000000000000000 x21: 0000000000000000 x22: 0000000000000001 x23: ffff8008f6133de0 x24: ffff00000930d40f x25: ffff8008fff300a0 x26: ffff8008fff34090 x27: ffff0000091e7000 x28: ffff8008f6130000 x29: ffff8008fff33fb0 Parking CPU 1 (Cell: "imx8") FATAL: instruction abort at 0x0 This issue is because the A53 CPU mmu table corrupt or not sync after CPU5 as "master" CPU finished the initialization or else. > >> >> If I use JTAG to let CPU 4/5 later than CPU0/1/2/3, no corrupt. >> >> Since there is a small hardware issue now, I could not make sure >> software/hardware >> issue. I'll continue debug. > >Well, there is always the risk that we need some special hardware quirk >workaround or that there is actually an architectural difference in the >A53/A72 setups that we still miss. A53 is pretty mature regarding >Jailhouse now, but A72 is new. > >[...] > >>>>> >>>>> Which RTOS do you have in mind, a commercial one or some open source >>>>> project? >>>> >>>> I would like to use open source projects, such as RTEMS. But graphic >>>> support >>>> is not that good. Also AArch64 support is not ready. >>>> Do you have some recommendation except RTEMS? And if using rtos as root >>>> cell, do you have >>>> some ideas how to proceed, seems jailhouse now heavily relys on Linux? >>> >>> I don't know which open source RTOS is already running well in AArch64 >>> mode. We were discussing Zephyr as potential boot loader for Jailhouse, >>> but that is also only supporting 32-bit mode so far. It seems to gain >>> x86-64 support soon, and that may open it up for AArch64 as well. >> >> As far as I know, Zephyr is mainly for IoT usage and ARM Cortex-A is not >> supported. I'll give a try on RTEMS first. > >Yes, there is some work missing to enable a Cortex-A in Zephyr, but >that's all not a lot of code - just check how small the inmates are that >Jailhouse provides for ARMv7 and v8. RTEMS should work but has its >oddities as well. I am not sure Zephyr is a good choice or not, I have little knowledge now. To use it in root cell, need to 1. Develop Cortex-A, to me it is Aarch64 2. Add PSCI 3. Develop jaihouse userspace tools, which may require posix API? Using A A53 CPU to run Zephyr sounds a waste of cpu resources :) Anyway Zephyr has a very active community. Thanks, Peng. > >Jan > >-- >Siemens AG, Corporate Technology, CT RDA ITP SES-DE >Corporate Competence Center Embedded Linux -- -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
