On 04/09/19 5:52 PM, Nikhil Devshatwar wrote: > Add the linux demo cell config for j721e-evm board. > Also add the required device tree for booting Linux kernel > in the inmate cell. > > This cell config acts as a reference for partitioning > devices across the 2 Linux cells. > This will be updated as support for more devices get added. > > Signed-off-by: Nikhil Devshatwar <[email protected]> > Signed-off-by: Lokesh Vutla <[email protected]> > --- > Changes from v2: > * Only add the DT entries for devices with stable bindings > * Organize the DTS to match the bus topology with upstream kernel > > Changes from v1: > * Split up the peripheral mem_region to match with kernel dts > * Add GPU, multimedia decoder and display devices > > configs/arm64/dts/inmate-k3-j721e-evm.dts | 285 > ++++++++++++++++++++++++++++++ > configs/arm64/k3-j721e-evm-linux-demo.c | 242 +++++++++++++++++++++++++ > 2 files changed, 527 insertions(+) > create mode 100644 configs/arm64/dts/inmate-k3-j721e-evm.dts > create mode 100644 configs/arm64/k3-j721e-evm-linux-demo.c > > diff --git a/configs/arm64/dts/inmate-k3-j721e-evm.dts > b/configs/arm64/dts/inmate-k3-j721e-evm.dts > new file mode 100644 > index 0000000..dfad5b3 > --- /dev/null > +++ b/configs/arm64/dts/inmate-k3-j721e-evm.dts > @@ -0,0 +1,285 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for J721E Jailhouse inmate kernel > + * > + * Copyright (C) 2016-2019 Texas Instruments Incorporated - > http://www.ti.com/ > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/k3.h> > + > +/ { > + model = "Texas Instruments J721E Inmate Model"; > + compatible = "ti,j721e-evm", "ti,j721e"; > + interrupt-parent = <&gic500>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial3 = &main_uart1; > + }; > + > + chosen { > + stdout-path = "serial3:115200n8"; > + }; > + > + hypervisor { > + compatible = "jailhouse,cell"; > + }; > + > + memory@8a0000000 { > + device_type = "memory"; > + reg = <0x8 0xa0000000 0x0 0x60000000>; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + cpu-map { > + cluster0: cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a72"; > + reg = <0x000>; > + device_type = "cpu"; > + enable-method = "psci"; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&L2_0>; > + }; > + }; > + > + L2_0: l2-cache0 { > + compatible = "cache"; > + cache-level = <2>; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <2048>; > + next-level-cache = <&msmc_l3>; > + }; > + > + msmc_l3: l3-cache0 { > + compatible = "cache"; > + cache-level = <3>; > + }; > + > + a72_timer0: timer-cl0-cpu0 { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ > + }; > + > + pmu: pmu { > + compatible = "arm,armv8-pmuv3"; > + /* Recommendation from GIC500 TRM Table A.3 */ > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + psci: psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + pci@76000000 { > + compatible = "pci-host-ecam-generic"; > + device_type = "pci"; > + bus-range = <0 0>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = > + <0 0 0 1 &gic500 0 0 GIC_SPI 163 IRQ_TYPE_EDGE_RISING>, > + <0 0 0 2 &gic500 0 0 GIC_SPI 164 IRQ_TYPE_EDGE_RISING>, > + <0 0 0 3 &gic500 0 0 GIC_SPI 165 IRQ_TYPE_EDGE_RISING>, > + <0 0 0 4 &gic500 0 0 GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; > + reg = <0x0 0x76000000 0x0 0x100000>; > + ranges = > + <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; > + }; > + > + cbass_main: interconnect@100000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* > ctrl mmr */ > + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* > GPIO */ > + <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* > serdes */ > + <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* > timesync router */ > + <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* > Most peripherals */ > + <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* > MAIN NAVSS */ > + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* > PCIe Core*/ > + <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* > PCIe DAT */ > + <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* > C71 */ > + <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* > C66_0 */ > + <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* > C66_1 */ > + <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* > GPU */ > + <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* > MSMC RAM */ > + > + /* MCUSS_WKUP Range */ > + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, > + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, > + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, > + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, > + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, > + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, > + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, > + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, > + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, > + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, > + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, > + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, > + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; > + > + cbass_mcu_wakeup: interconnect@28380000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 > 0x03880000>, /* MCU NAVSS*/ > + <0x00 0x40200000 0x00 0x40200000 0x00 > 0x00998400>, /* First peripheral window */ > + <0x00 0x40f00000 0x00 0x40f00000 0x00 > 0x00020000>, /* CTRL_MMR0 */ > + <0x00 0x41000000 0x00 0x41000000 0x00 > 0x00020000>, /* MCU R5F Core0 */ > + <0x00 0x41400000 0x00 0x41400000 0x00 > 0x00020000>, /* MCU R5F Core1 */ > + <0x00 0x41c00000 0x00 0x41c00000 0x00 > 0x00100000>, /* MCU SRAM */ > + <0x00 0x42040000 0x00 0x42040000 0x00 > 0x03ac2400>, /* WKUP peripheral window */ > + <0x00 0x45100000 0x00 0x45100000 0x00 > 0x00c24000>, /* MMRs, remaining NAVSS */ > + <0x00 0x46000000 0x00 0x46000000 0x00 > 0x00200000>, /* CPSW */ > + <0x00 0x47000000 0x00 0x47000000 0x00 > 0x00068400>, /* OSPI register space */ > + <0x00 0x50000000 0x00 0x50000000 0x00 > 0x10000000>, /* FSS OSPI0/1 data region 0 */ > + <0x05 0x00000000 0x05 0x00000000 0x01 > 0x00000000>, /* FSS OSPI0 data region 3 */ > + <0x07 0x00000000 0x07 0x00000000 0x01 > 0x00000000>; /* FSS OSPI1 data region 3*/ > + }; > + }; > +}; > + > +&cbass_main { > + > + gic500: interrupt-controller@1800000 { > + compatible = "arm,gic-v3"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ > + <0x00 0x01900000 0x00 0x100000>; /* GICR */ > + > + /* vcpumntirq: virtual CPU interface maintenance interrupt */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + cbass_main_navss: interconnect0 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + main_navss_intr: interrupt-controller1 { > + compatible = "ti,sci-intr"; > + interrupt-controller; > + interrupt-parent = <&gic500>; > + #interrupt-cells = <2>; > + ti,sci = <&dmsc>; > + ti,sci-dst-id = <14>; > + ti,sci-rm-range-girq = <4>; > + }; > + > + main_udmass_inta: interrupt-controller@33d00000 { > + compatible = "ti,sci-inta"; > + reg = <0x0 0x33d00000 0x0 0x100000>; > + interrupt-controller; > + interrupt-parent = <&main_navss_intr>; > + msi-controller; > + ti,sci = <&dmsc>; > + ti,sci-dev-id = <209>; > + ti,sci-rm-range-vint = <0xa>; > + ti,sci-rm-range-global-event = <0xd>; > + }; > + }; > + > + secure_proxy_main: mailbox@32c00000 { > + compatible = "ti,am654-secure-proxy"; > + #mbox-cells = <1>; > + reg-names = "target_data", "rt", "scfg"; > + reg = <0x00 0x32c00000 0x00 0x100000>, > + <0x00 0x32400000 0x00 0x100000>, > + <0x00 0x32800000 0x00 0x100000>; > + interrupt-names = "rx_011"; > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + main_pmx0: pinmux@11c000 { > + compatible = "pinctrl-single"; > + /* Proxy 0 addressing */ > + reg = <0x0 0x11c000 0x0 0x2b4>; > + #pinctrl-cells = <1>; > + pinctrl-single,register-width = <32>; > + pinctrl-single,function-mask = <0xffffffff>; > + }; > + > + main_uart1: serial@2810000 { > + compatible = "ti,j721e-uart", "ti,am654-uart"; > + reg = <0x00 0x02810000 0x00 0x100>; > + reg-shift = <2>; > + reg-io-width = <4>; > + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <48000000>; > + current-speed = <115200>; > + power-domains = <&k3_pds 278>; Power-domain cells are defined as 2 but you are using only 1 cell. Isn't compiler giving a warning? Thanks and regards, Lokesh > + clocks = <&k3_clks 278 0>; > + clock-names = "fclk"; > + }; > +}; > + > +&cbass_mcu_wakeup { > + dmsc: dmsc@44083000 { > + compatible = "ti,k2g-sci"; > + ti,host-id = <13>; > + > + mbox-names = "rx", "tx"; > + > + mboxes= <&secure_proxy_main 16>, > + <&secure_proxy_main 18>; > + > + reg-names = "debug_messages"; > + reg = <0x00 0x44083000 0x0 0x1000>; > + > + k3_pds: power-controller { > + compatible = "ti,sci-pm-domain"; > + #power-domain-cells = <2>; > + }; > + > + k3_clks: clocks { > + compatible = "ti,k2g-sci-clk"; > + #clock-cells = <2>; > + }; > + > + k3_reset: reset-controller { > + compatible = "ti,sci-reset"; > + #reset-cells = <2>; > + }; > + }; > + > + wkup_pmx0: pinmux@4301c000 { > + compatible = "pinctrl-single"; > + /* Proxy 0 addressing */ > + reg = <0x00 0x4301c000 0x00 0x178>; > + #pinctrl-cells = <1>; > + pinctrl-single,register-width = <32>; > + pinctrl-single,function-mask = <0xffffffff>; > + }; > +}; > \ No newline at end of file > diff --git a/configs/arm64/k3-j721e-evm-linux-demo.c > b/configs/arm64/k3-j721e-evm-linux-demo.c > new file mode 100644 > index 0000000..347ae0e > --- /dev/null > +++ b/configs/arm64/k3-j721e-evm-linux-demo.c > @@ -0,0 +1,242 @@ > +/* > + * Jailhouse, a Linux-based partitioning hypervisor > + * > + * Configuration for Linux inmate on J721E based platforms > + * 1 CPUs, 512MB RAM, 1 serial port > + * > + * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com/ > + * > + * Authors: > + * Nikhil Devshatwar <[email protected]> > + * Lokesh Vutla <[email protected]> > + * > + * This work is licensed under the terms of the GNU GPL, version 2. See > + * the COPYING file in the top-level directory. > + */ > + > +#include <jailhouse/types.h> > +#include <jailhouse/cell-config.h> > + > +#ifndef CONFIG_INMATE_BASE > +#define CONFIG_INMATE_BASE 0x0000000 > +#endif > + > +struct { > + struct jailhouse_cell_desc cell; > + __u64 cpus[1]; > + struct jailhouse_memory mem_regions[20]; > + struct jailhouse_irqchip irqchips[3]; > + struct jailhouse_pci_device pci_devices[1]; > +} __attribute__((packed)) config = { > + .cell = { > + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, > + .revision = JAILHOUSE_CONFIG_REVISION, > + .name = "k3-j721e-evm-linux-demo", > + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG, > + > + .cpu_set_size = sizeof(config.cpus), > + .num_memory_regions = ARRAY_SIZE(config.mem_regions), > + .num_irqchips = ARRAY_SIZE(config.irqchips), > + .num_pci_devices = ARRAY_SIZE(config.pci_devices), > + .cpu_reset_address = 0x0, > + .vpci_irq_base = 195 - 32, > + .console = { > + .address = 0x2810000, > + .divider = 0x1b, > + .type = JAILHOUSE_CON_TYPE_8250, > + .flags = JAILHOUSE_CON_ACCESS_MMIO | > + JAILHOUSE_CON_REGDIST_4, > + }, > + }, > + > + .cpus = { > + 0x2, > + }, > + > + .mem_regions = { > + /* IVSHMEM shared memory region for 00:00.0 */ { > + .phys_start = 0x89fe00000, > + .virt_start = 0x89fe00000, > + .size = 0x100000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_ROOTSHARED, > + }, > + /* ctrl mmr */ { > + .phys_start = 0x00100000, > + .virt_start = 0x00100000, > + .size = 0x00020000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, > + }, > + /* Main.uart1 */ { > + .phys_start = 0x02810000, > + .virt_start = 0x02810000, > + .size = 0x1000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* sdhci0 */ { > + .phys_start = 0x4f80000, > + .virt_start = 0x4f80000, > + .size = 0x1000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, > + }, > + /* sdhci0 */ { > + .phys_start = 0x4f88000, > + .virt_start = 0x4f88000, > + .size = 0x1000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, > + }, > + /* main sproxy target_data host_id=A72_3 */ { > + .phys_start = 0x3240f000, > + .virt_start = 0x3240f000, > + .size = 0x05000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* main sproxy rt host_id=A72_3 */ { > + .phys_start = 0x3280f000, > + .virt_start = 0x3280f000, > + .size = 0x05000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* main sproxy scfg host_id=A72_3 */ { > + .phys_start = 0x32c0f000, > + .virt_start = 0x32c0f000, > + .size = 0x05000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* D552 decoder */ { > + .phys_start = 0x4300000, > + .virt_start = 0x4300000, > + .size = 0x100000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* GPU */ { > + .phys_start = 0x4e20000000, > + .virt_start = 0x4e20000000, > + .size = 0x80000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* dss.common_s1 */ { > + .phys_start = 0x4B00000, > + .virt_start = 0x4B00000, > + .size = 0x00010000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* dss.vidl1 */ { > + .phys_start = 0x4A20000, > + .virt_start = 0x4A20000, > + .size = 0x00010000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* dss.ovr1 */ { > + .phys_start = 0x4A70000, > + .virt_start = 0x4A70000, > + .size = 0x00010000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* dss.vp1 */ { > + .phys_start = 0x4A80000, > + .virt_start = 0x4A80000, > + .size = 0x00010000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* serdes 10G */ { > + .phys_start = 0x05050000, > + .virt_start = 0x05050000, > + .size = 0x10000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* DSS_EDP0_V2A_CORE_VP_REGS_AP */ { > + .phys_start = 0x0A000000, > + .virt_start = 0x0A000000, > + .size = 0x31000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* DSS_EDP0_INTG_CFG_VP */ { > + .phys_start = 0x04F40000, > + .virt_start = 0x04F40000, > + .size = 0x1000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_IO, > + }, > + /* linux-loader space */ { > + .phys_start = 0x89ff00000, > + .virt_start = 0x0, > + .size = 0x10000, /* 64KB */ > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, > + }, > + /* RAM. */ { > + .phys_start = 0x8a0000000, > + .virt_start = 0x8a0000000, > + .size = 0x60000000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA | > + JAILHOUSE_MEM_LOADABLE, > + }, > + /* communication region */ { > + .virt_start = 0x80000000, > + .size = 0x00001000, > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | > + JAILHOUSE_MEM_COMM_REGION, > + }, > + }, > + > + .irqchips = { > + /* > + * offset = (SPI_NR + 32 - base) / 32 > + * bit = (SPI_NR + 32 - base) % 32 > + */ > + { > + .address = 0x01800000, > + .pin_base = 32, > + /* gpu, sdhci0, sproxy_rx_016 */ > + .pin_bitmap = { > + 0x1000008, 0x80, 0x0, 0, > + }, > + }, > + { > + .address = 0x01800000, > + .pin_base = 160, > + /* d5520, vpci, main_uart1 */ > + .pin_bitmap = { > + 0x0, 0x100008, 0x2, 0, > + }, > + }, > + { > + .address = 0x01800000, > + .pin_base = 544, > + /* dss common_s1, mhdp */ > + .pin_bitmap = { > + 0x0, 0x0, 0x10000000, 0x40, > + }, > + }, > + }, > + > + .pci_devices = { > + /* 00:00.0 */ { > + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, > + .bdf = 0x00, > + .bar_mask = { > + 0xffffff00, 0xffffffff, 0x00000000, > + 0x00000000, 0x00000000, 0x00000000, > + }, > + .shmem_region = 0, > + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH, > + }, > + }, > +}; > -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. 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Re: [PATCH v3 4/4] configs: arm64: Add Linux demo for j721-evm board
'Lokesh Vutla' via Jailhouse Wed, 04 Sep 2019 06:42:40 -0700
- [PATCH v3 0/4] Initial support for j721-... 'Nikhil Devshatwar' via Jailhouse
- [PATCH v3 2/4] configs: arm64: Add ... 'Nikhil Devshatwar' via Jailhouse
- Re: [PATCH v3 2/4] configs: arm... 'Lokesh Vutla' via Jailhouse
- Re: [PATCH v3 2/4] configs:... 'Nikhil Devshatwar' via Jailhouse
- [PATCH v3 3/4] configs: arm64: Add ... 'Nikhil Devshatwar' via Jailhouse
- [PATCH v3 4/4] configs: arm64: Add ... 'Nikhil Devshatwar' via Jailhouse
- Re: [PATCH v3 4/4] configs: arm... 'Lokesh Vutla' via Jailhouse
- Re: [PATCH v3 4/4] configs:... 'Nikhil Devshatwar' via Jailhouse
- [PATCH v3 1/4] inmates: uart-8250: ... 'Nikhil Devshatwar' via Jailhouse
