I want to communicate between two inmate cell for this I prepared cell 
configuration as listed below.
when I tried to load both inmate it displayed EBUSY error. 
1) How can I define same shared  memory for both inmate? 
2)how can I communicate between two inmate. 
3) it is stated on intercell communication document "you can go ahead and 
connect two non-root cell and run the ivshmem-demo. They will send 
interrupts to each other." That means, we can run ivshmem-demo on both cell 
and send interrupts between inmate cell, yes?

=>In the inter-cell communication document it is stated both cell should 
have same memory region, same ivshmem-type, and same bdf. But when defining 
same pci-device to both cell it showed EBUSY error. 
please help me on this?
ROOT CELL: (only relevant part is copied)

/* IVHSMEM  1*/ {
                        .phys_start = 0x17ba00000,
                        .virt_start = 0x17ba00000,
                        .size = 0x100000,
                        .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE ,

                },

        /* IVHSMEM  2*/ {
                        .phys_start = 0x17bd00000,
                        .virt_start = 0x17bd00000,
                        .size = 0x100000,
                        .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE ,
                },

    },

    .irqchips = {
        /* GIC */ {
            .address = 0x50041000,
            .pin_base = 32,
            .pin_bitmap = {
                0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
            },
        },
        /* GIC */ {
            .address = 0x50041000,
            .pin_base = 160,
            .pin_bitmap = {
                0xffffffff, 0xffffffff, 0xffffffff
            },
        },
    },

    .pci_devices = {
                {
                        .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
                        .bdf = 0x0 << 3,
                        .bar_mask = {
                                0xffffff00, 0xffffffff, 0x00000000,
                                0x00000000, 0x00000000, 0x00000000,
                        },

            /*num_msix_vectors needs to be 0 for INTx operation*/
                        .num_msix_vectors = 0,
            .shmem_region = 42,
            .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,

                },

        {
                        .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
                        .bdf = 0xf << 3,
                        .bar_mask = {
                                0xffffff00, 0xffffffff, 0x00000000,
                                0x00000000, 0x00000000, 0x00000000,
                        },

                        /*num_msix_vectors needs to be 0 for INTx 
operation*/
                        .num_msix_vectors = 0,
                        .shmem_region = 43,
                        .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,

                },
        }

INMATE 1 Configuration ::::::::::::::::::

struct {
    struct jailhouse_cell_desc cell;
    __u64 cpus[1];
    struct jailhouse_memory mem_regions[5];
    struct jailhouse_irqchip irqchips[2];
    struct jailhouse_pci_device pci_devices[1];
} __attribute__((packed)) config = {
    .cell = {
        .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
        .revision = JAILHOUSE_CONFIG_REVISION,
        .name = "inmate1",
        .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
        .cpu_set_size = sizeof(config.cpus),
        .num_memory_regions = ARRAY_SIZE(config.mem_regions),
        .num_irqchips = ARRAY_SIZE(config.irqchips),
        .num_pci_devices = ARRAY_SIZE(config.pci_devices),
        .vpci_irq_base = 186,
    },

    .cpus = {
        0x8,
    },

    .mem_regions = {
        /* UART */ {
            .phys_start = 0x70006000,
            .virt_start = 0x70006000,
            .size = 0x1000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                JAILHOUSE_MEM_IO,
        },
        /* RAM */ {
            .phys_start = 0x17bfe0000,
            .virt_start = 0,
            .size = 0x00010000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
        },
        /* communication region */ {
            .virt_start = 0x80000000,
            .size = 0x00001000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                JAILHOUSE_MEM_COMM_REGION,
        },
        /* IVHSMEM  1*/ {
                        .phys_start = 0x17ba00000,
                        .virt_start = 0x17ba00000,
                        .size = 0x100000,
                        .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                                JAILHOUSE_MEM_ROOTSHARED,

                },
    },

    .irqchips = {
        /* GIC */ {
            .address = 0x50041000,
                        .pin_base = 32,
                        /* Interrupts:
                           46 for UART C  */
                        .pin_bitmap = {
                0,
                1<<(46-32)
                        },
                },

        /* GIC */ {
            .address = 0x50041000,
                        .pin_base = 160,
                        /* Interrupts:
                           186 for IVSHMEM,
                           belongs to the bare metal cell  */
                        .pin_bitmap = {
                0,
                3<<(186-160)
                        },

                },
        },

    .pci_devices = {
                {
                        .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
                        .bdf = 0x0 << 3,
                        .bar_mask = {
                                0xffffff00, 0xffffffff, 0x00000000,
                                0x00000000, 0x00000000, 0x00000000,
                        },
            /* num_msix_vectors needs to be 0 for INTx operation*/
            .num_msix_vectors = 0, 
                        .shmem_region = 3, /* must be no of IVSHMEM region 
above */
            .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
                },
         
        },
};

INMATE2 Configuration:::::::::::::::::::::::::::

struct {
    struct jailhouse_cell_desc cell;
    __u64 cpus[1];
    struct jailhouse_memory mem_regions[5];
    struct jailhouse_irqchip irqchips[2];
    struct jailhouse_pci_device pci_devices[1];
} __attribute__((packed)) config = {
    .cell = {
        .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
        .revision = JAILHOUSE_CONFIG_REVISION,
        .name = "inmate2",
        .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,

        .cpu_set_size = sizeof(config.cpus),
        .num_memory_regions = ARRAY_SIZE(config.mem_regions),
        .num_irqchips = ARRAY_SIZE(config.irqchips),
        .num_pci_devices = ARRAY_SIZE(config.pci_devices),
        /*On Jetson TX1 the IRQs from 212 to 223 are not assigned.
        The bare metal cell will use IRQs from 218 to 223.
        Note: Jailhouse adds 32 (GIC's SPI) to the .vpci_irq_base,
        so 190 is the base value*/
        .vpci_irq_base = 190,
    },

    .cpus = {
        0x2,
    },

    .mem_regions = {
        /* UART */ {
            .phys_start = 0x70006000,
            .virt_start = 0x70006000,
            .size = 0x1000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                JAILHOUSE_MEM_IO,
        },
        /* RAM */ {
            .phys_start = 0x17bfc0000,
            .virt_start = 0,
            .size = 0x00010000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
        },
        /* communication region */ {
            .virt_start = 0x80000000,
            .size = 0x00001000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                JAILHOUSE_MEM_COMM_REGION,
        },

       /* IVHSMEM  1*/ {
                        .phys_start = 0x17ba00000,
                        .virt_start = 0x17ba00000,
                        .size = 0x100000,
                        .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                                JAILHOUSE_MEM_ROOTSHARED,

                },
    },

    .irqchips = {
        /* GIC */ {
            .address = 0x50041000,
                        .pin_base = 32,
                        /* Interrupts:
                           36 for UART C  */
                        .pin_bitmap = {
                0,
                1<<(36-32)
                        },
                },

        /* GIC */ {
            .address = 0x50041000,
                        .pin_base = 160,
                        /* Interrupts:
                           190 for IVSHMEM,
                           belongs to the bare metal cell  */
                        .pin_bitmap = {
                0,
                3<<(190-160)
                        },
                },
        },

    .pci_devices = {

         {
                        .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
                        .bdf = 0x0 << 3,
                        .bar_mask = {
                                0xffffff00, 0xffffffff, 0x00000000,
                                0x00000000, 0x00000000, 0x00000000,
                        },
                        /* num_msix_vectors needs to be 0 for INTx 
operation*/
                        .num_msix_vectors = 0,
                        .shmem_region = 3, /* must be no of IVSHMEM region 
above */
                        .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
                },
        },
};

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