Branch: refs/heads/next
Home: https://github.com/siemens/jailhouse
Commit: dcc62c3f365ef06c4d701a77aed9abfb204b0b02
https://github.com/siemens/jailhouse/commit/dcc62c3f365ef06c4d701a77aed9abfb204b0b02
Author: Alice Guo <alice....@nxp.com>
Date: 2020-08-18 (Tue, 18 Aug 2020)
Changed paths:
M hypervisor/arch/arm-common/control.c
M hypervisor/arch/arm-common/include/asm/control.h
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm64/control.c
M hypervisor/arch/arm64/entry.S
M hypervisor/arch/arm64/include/asm/sysregs.h
M include/jailhouse/cell-config.h
Log Message:
-----------
arm64: support inmate cell in AArch32 mode
An AArch64 hypervisor can host both AArch32 and AArch64 virtual machines
at the same time. If the inmate cell wants to run in AArch32 mode, the
assigned cpu must change to AArch32. Because AArch64 hypervisor and
AArch64 root cell are used, when the AArch32 inmate cell is destroyed,
cpu owned by inmate cell will be reassigned to AArch64 root cell, switch
the cpu back to AArch64.
The following is a summary of some of the points when supporting inmate
cell in AArch32 mode:
Define a macro "JAILHOUSE_CELL_AARCH32" to indicate AArch32 execution
state. Add this macro to flags of struct jailhouse_cell_desc, and you can
use it to indicate whether a cell is AArch32.
Add "bool aarch32" as second parameter to arm_cpu_reset(), and can use
it to pass execution state. If aarch32 equals true, switch to AArch32.
When an exception occurs, the processor must execute handler code which
corresponds to the exception. When the exception is being taken at a
lower Exception level, the execution state of the next lower level
(AArch64 or AArch32) will be used. Fill exception handling functions for
Lower EL using AArch32 in hypervisor/arch/arm64/entry.S.
Configure the registers related to changing execution state. If a cell
is AArch32, SPSR_EL2.M[4] will be set to 0b1 which means AArch32
execution state, SPSR_EL2.M[3:0] will be set to 0b0011 which means
Supervisor, and HCR_EL2.RW will be set to 0b0 which means lower levels
are all AArch32. If a cell is AArch64, make sure HCR_EL2.RW is 0 and the
other registers are configured according to the previous code.
After Linux operating system boots up, execute the following commands to
use AArch32 virtual machine on the i.MX8DXL:
./jailhouse enable imx8dxl.cell
./jailhouse cell create imx8dxl-gic-demo-aarch32.cell
./jailhouse cell load 1 gic-demo.bin (32-bit)
./jailhouse cell start 1
Signed-off-by: Alice Guo <alice....@nxp.com>
[Jan: style fixes]
Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>
Commit: 20015a7645ac9ba8123a3f2f10a003bbe084149f
https://github.com/siemens/jailhouse/commit/20015a7645ac9ba8123a3f2f10a003bbe084149f
Author: Alice Guo <alice....@nxp.com>
Date: 2020-08-18 (Tue, 18 Aug 2020)
Changed paths:
M hypervisor/arch/arm-common/gic-v3.c
Log Message:
-----------
arm-common: gic-v3: Add support for accessing GICR_TYPER high word separately
This is needed for 32-bit guests that cannot issue 64-bit accesses, thus
will trigger two separate 32-bit accesses.
Signed-off-by: Alice Guo <alice....@nxp.com>
[Jan: replaced subject and commit message]
Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>
Commit: 1c70fb3943f09e35ece0d2b739e6d25bc9566baa
https://github.com/siemens/jailhouse/commit/1c70fb3943f09e35ece0d2b739e6d25bc9566baa
Author: Alice Guo <alice....@nxp.com>
Date: 2020-08-18 (Tue, 18 Aug 2020)
Changed paths:
M inmates/lib/arm-common/gic-v3.c
M inmates/lib/arm/include/asm/sysregs.h
M inmates/lib/arm64/include/asm/sysregs.h
Log Message:
-----------
inmates: gic-v3: solve 32-bit incompatibility problems in gic_v3_init()
When the inmate cell is in AArch32 execution state, using mmio_read64()
to obtain the value of GICR_TYPER will cause error because mmio_read64()
generates "ldrd" instruction when compiling 32-bit gic_demo.bin, and
"ldrd" belongs to A64 assembly language which is cannot be used in
AArch32. So use mmio_read32() to read 64-bit GICR_ TYPER in twice.
In ARMv8-A, AArch64 state supports four levels of affinity. but AArch32
state can only support three levels of affinity. So use MPIDR_CPUID_MASK
to set bit[31:24] of mpidr to be 0, and ensure the correct mpidr.
Signed-off-by: Alice Guo <alice....@nxp.com>
[Jan: slightly improved subject]
Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>
Commit: f34cb118a0eda21d611c4bbb0f44373aa012e5eb
https://github.com/siemens/jailhouse/commit/f34cb118a0eda21d611c4bbb0f44373aa012e5eb
Author: Alice Guo <alice....@nxp.com>
Date: 2020-08-18 (Tue, 18 Aug 2020)
Changed paths:
A configs/arm64/imx8dxl-inmate-demo-aarch32.c
A configs/arm64/imx8dxl-inmate-demo.c
A configs/arm64/imx8dxl.c
Log Message:
-----------
configs: arm64: imx8dxl: add cell configuration files
Add "imx8dxl-inmate-demo-aarch32.c" to support AArch32 VM on the imx8dxl
platform. Distinguish whether it is AArch32 inmate cell by the macro
JAILHOUSE_CELL_AARCH32.
Add "imx8dxl-inmate-demo.c" for AArch64 VM.
"imx8dxl.c" is used for the root cell.
Signed-off-by: Alice Guo <alice....@nxp.com>
Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>
Compare:
https://github.com/siemens/jailhouse/compare/f02a43a5fb3c...f34cb118a0ed
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