Add root cell, inmate cell and Linux demo cell configuration files for NXP
LS1028ARDB platform.
Signed-off-by: Anda-Alexandra Dorneanu <anda-alexandra.dorne...@nxp.com>
---
configs/arm64/ls1028a-rdb-inmate-demo.c | 122 +++++
configs/arm64/ls1028a-rdb-linux-demo.c | 142 ++++++
configs/arm64/ls1028a-rdb.c | 609 ++++++++++++++++++++++++
3 files changed, 873 insertions(+)
create mode 100644 configs/arm64/ls1028a-rdb-inmate-demo.c
create mode 100644 configs/arm64/ls1028a-rdb-linux-demo.c
create mode 100644 configs/arm64/ls1028a-rdb.c
diff --git a/configs/arm64/ls1028a-rdb-inmate-demo.c
b/configs/arm64/ls1028a-rdb-inmate-demo.c
new file mode 100644
index 00000000..8b45a9ed
--- /dev/null
+++ b/configs/arm64/ls1028a-rdb-inmate-demo.c
@@ -0,0 +1,122 @@
+/*
+ * Configuration for LS1028ARDB board - inmate demo
+ *
+ * Copyright NXP 2021
+ *
+ * Authors:
+ * Anda-Alexandra Dorneanu <anda-alexandra.dorne...@nxp.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[7];
+ struct jailhouse_irqchip irqchips[2];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "inmate-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .vpci_irq_base = 40 - 32,
+
+ .console = {
+ .address = 0x21c0600,
+ .divider = 0x6d,
+ .type = JAILHOUSE_CON_TYPE_8250,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_1,
+ },
+ },
+
+ .cpus = {
+ 0x2,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory region for 00:00.0 */ {
+ .phys_start = 0xfb700000,
+ .virt_start = 0xfb700000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb701000,
+ .virt_start = 0xfb701000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb70a000,
+ .virt_start = 0xfb70a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb70c000,
+ .virt_start = 0xfb70c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* DUART1 */ {
+ .phys_start = 0x21c0000,
+ .virt_start = 0x21c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* RAM */ {
+ .phys_start = 0xc0000000,
+ .virt_start = 0,
+ .size = 0x00010000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */ {
+ .virt_start = 0x80000000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */ {
+ .address = 0x6000000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 1 << (40 - 32),
+ 0,
+ 0,
+ 0,
+ },
+ },
+ },
+
+ .pci_devices = {
+ { /* IVSHMEM 00:00.0 */
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 0,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 1,
+ .shmem_peers = 1,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ },
+};
diff --git a/configs/arm64/ls1028a-rdb-linux-demo.c
b/configs/arm64/ls1028a-rdb-linux-demo.c
new file mode 100644
index 00000000..e2cb01af
--- /dev/null
+++ b/configs/arm64/ls1028a-rdb-linux-demo.c
@@ -0,0 +1,142 @@
+/*
+ * Configuration for LS1028ARDB board - linux demo
+ *
+ * Copyright 2021 NXP
+ *
+ * Authors:
+ * Anda-Alexandra Dorneanu <anda-alexandra.dorne...@nxp.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[13];
+ struct jailhouse_irqchip irqchips[2];
+ struct jailhouse_pci_device pci_devices[2];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "linux-inmate-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .vpci_irq_base = 40 - 32,
+ },
+
+ .cpus = {
+ 0x2,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory region for 00:00.0 */ {
+ .phys_start = 0xfb700000,
+ .virt_start = 0xfb700000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb701000,
+ .virt_start = 0xfb701000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb70a000,
+ .virt_start = 0xfb70a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb70c000,
+ .virt_start = 0xfb70c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* IVSHMEM shared memory regions for 00:01.0 */
+ JAILHOUSE_SHMEM_NET_REGIONS(0xfb800000, 1),
+ /* DUART1 */ {
+ .phys_start = 0x21c0000,
+ .virt_start = 0x21c0000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* clockgen */ {
+ .phys_start = 0x01300000,
+ .virt_start = 0x01300000,
+ .size = 0xa0000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* RAM */ {
+ .phys_start = 0xbf900000,
+ .virt_start = 0,
+ .size = 0x00010000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* RAM */ {
+ .phys_start = 0xc0000000,
+ .virt_start = 0xc0000000,
+ .size = 0x3b500000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
+ JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */ {
+ .virt_start = 0x80000000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */ {
+ .address = 0x6000000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 1 << (40 - 32) | 1 << (41 - 32) |
+ 1 << (42 - 32) | 1 << (43 - 32),
+ 0,
+ 0,
+ 0,
+ },
+ },
+ },
+
+ .pci_devices = {
+ { /* IVSHMEM 00:00.0 */
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 0,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 1,
+ .shmem_peers = 2,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ { /* IVSHMEM 00:01.0 */
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 0,
+ .bdf = 1 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 4,
+ .shmem_dev_id = 1,
+ .shmem_peers = 2,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
+ },
+ },
+};
diff --git a/configs/arm64/ls1028a-rdb.c b/configs/arm64/ls1028a-rdb.c
new file mode 100644
index 00000000..6027772b
--- /dev/null
+++ b/configs/arm64/ls1028a-rdb.c
@@ -0,0 +1,609 @@
+/*
+ * Configuration for LS1028ARDB board
+ *
+ * Copyright 2021 NXP
+ *
+ * Authors:
+ * Anda-Alexandra Dorneanu <anda-alexandra.dorne...@nxp.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[76];
+ struct jailhouse_irqchip irqchips[2];
+ struct jailhouse_pci_device pci_devices[2];
+} __attribute__((packed)) config = {
+ .header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory = {
+ .phys_start = 0xfba00000,
+ .size = 0x00400000,
+ },
+ .debug_console = {
+ .address = 0x21c0500,
+ .size = 0x100,
+ .type = JAILHOUSE_CON_TYPE_8250,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_1,
+ },
+ .platform_info = {
+ .pci_mmconfig_base = 0xfb500000,
+ .pci_mmconfig_end_bus = 0,
+ .pci_is_virtual = 1,
+ .pci_domain = -1,
+
+ .arm = {
+ .gic_version = 3,
+ .gicd_base = 0x6000000,
+ .gicr_base = 0x6040000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "ls1028a",
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .vpci_irq_base = 50 - 32,
+ },
+ },
+
+ .cpus = {
+ 0x3,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory region for 00:00.0 */ {
+ .phys_start = 0xfb700000,
+ .virt_start = 0xfb700000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ {
+ .phys_start = 0xfb701000,
+ .virt_start = 0xfb701000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ {
+ .phys_start = 0xfb70a000,
+ .virt_start = 0xfb70a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ {
+ .phys_start = 0xfb70c000,
+ .virt_start = 0xfb70c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ /* IVSHMEM shared memory regions for 00:01.0 */
+ JAILHOUSE_SHMEM_NET_REGIONS(0xfb800000, 0),
+ /* RAM - 1GB - root cell */ {
+ .phys_start = 0x80000000,
+ .virt_start = 0x80000000,
+ .size = 0x40000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* DRAM2 2GB */ {
+ .phys_start = 0x2080000000,
+ .virt_start = 0x2080000000,
+ .size = 0x80000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* RAM - ~1GB - inmate */ {
+ .phys_start = 0xc0000000,
+ .virt_start = 0xc0000000,
+ .size = 0x3b500000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* DDR memory controller */ {
+ .phys_start = 0x01080000,
+ .virt_start = 0x01080000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* dcfg */ {
+ .phys_start = 0x01e00000,
+ .virt_start = 0x01e00000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* rst */ {
+ .phys_start = 0x01e60000,
+ .virt_start = 0x01e60000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* scfg */ {
+ .phys_start = 0x01fc0000,
+ .virt_start = 0x01fc0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* clockgen */ {
+ .phys_start = 0x01300000,
+ .virt_start = 0x01300000,
+ .size = 0xa0000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* i2c0 */ {
+ .phys_start = 0x02000000,
+ .virt_start = 0x02000000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* i2c1 */ {
+ .phys_start = 0x02010000,
+ .virt_start = 0x02010000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* i2c2 */ {
+ .phys_start = 0x02020000,
+ .virt_start = 0x02020000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* i2c3 */ {
+ .phys_start = 0x02030000,
+ .virt_start = 0x02030000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* i2c4 */ {
+ .phys_start = 0x02040000,
+ .virt_start = 0x02040000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* i2c5 */ {
+ .phys_start = 0x02050000,
+ .virt_start = 0x02050000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* i2c6 */ {
+ .phys_start = 0x02060000,
+ .virt_start = 0x02060000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* i2c7 */ {
+ .phys_start = 0x02070000,
+ .virt_start = 0x02070000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* fspi */ {
+ .phys_start = 0x020c0000,
+ .virt_start = 0x020c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* dspi0 */ {
+ .phys_start = 0x02100000,
+ .virt_start = 0x02100000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* dspi1 */ {
+ .phys_start = 0x02110000,
+ .virt_start = 0x02110000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* dspi2 */ {
+ .phys_start = 0x02120000,
+ .virt_start = 0x02120000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* esdhc */ {
+ .phys_start = 0x02140000,
+ .virt_start = 0x02140000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* esdhc1 */ {
+ .phys_start = 0x02150000,
+ .virt_start = 0x02150000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* can0 */ {
+ .phys_start = 0x02180000,
+ .virt_start = 0x02180000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* can1 */ {
+ .phys_start = 0x02190000,
+ .virt_start = 0x02190000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* duart0 */ {
+ .phys_start = 0x021c0000,
+ .virt_start = 0x021c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* lpuart0 */ {
+ .phys_start = 0x02260000,
+ .virt_start = 0x02260000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* lpuart1 */ {
+ .phys_start = 0x02270000,
+ .virt_start = 0x02270000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* lpuart2 */ {
+ .phys_start = 0x02280000,
+ .virt_start = 0x02280000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* lpuart3 */ {
+ .phys_start = 0x02290000,
+ .virt_start = 0x02290000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* lpuart4 */ {
+ .phys_start = 0x022a0000,
+ .virt_start = 0x022a0000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* lpuart5 */ {
+ .phys_start = 0x022b0000,
+ .virt_start = 0x022b0000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* edma0 */ {
+ .phys_start = 0x022c0000,
+ .virt_start = 0x022c0000,
+ .size = 0x30000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* gpio1 */ {
+ .phys_start = 0x02300000,
+ .virt_start = 0x02300000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* gpio2 */ {
+ .phys_start = 0x02310000,
+ .virt_start = 0x02310000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* gpio3 */ {
+ .phys_start = 0x02320000,
+ .virt_start = 0x02320000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* usb0 */ {
+ .phys_start = 0x03100000,
+ .virt_start = 0x03100000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* usb1 */ {
+ .phys_start = 0x03110000,
+ .virt_start = 0x03110000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* sata */ {
+ .phys_start = 0x03200000,
+ .virt_start = 0x03200000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie1 */ {
+ .phys_start = 0x03400000,
+ .virt_start = 0x03400000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie2 */ {
+ .phys_start = 0x03500000,
+ .virt_start = 0x03500000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie2 pf0 */ {
+ .phys_start = 0x035c0000,
+ .virt_start = 0x035c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie1 host bridge */ {
+ .phys_start = 0x8000000000,
+ .virt_start = 0x8000000000,
+ .size = 0x800000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie2 host bridge */ {
+ .phys_start = 0x8800000000,
+ .virt_start = 0x8800000000,
+ .size = 0x800000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* gic its */ {
+ .phys_start = 0x06020000,
+ .virt_start = 0x06020000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* crypto */ {
+ .phys_start = 0x08000000,
+ .virt_start = 0x08000000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wdog0 */ {
+ .phys_start = 0x0c000000,
+ .virt_start = 0x0c000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wdog1 */ {
+ .phys_start = 0x0c010000,
+ .virt_start = 0x0c010000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* gpu */ {
+ .phys_start = 0x0f0c0000,
+ .virt_start = 0x0f0c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* sai1 */ {
+ .phys_start = 0x0f100000,
+ .virt_start = 0x0f100000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* sai2 */ {
+ .phys_start = 0x0f110000,
+ .virt_start = 0x0f110000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* sai3 */ {
+ .phys_start = 0x0f120000,
+ .virt_start = 0x0f120000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* sai4 */ {
+ .phys_start = 0x0f130000,
+ .virt_start = 0x0f130000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* sai5 */ {
+ .phys_start = 0x0f140000,
+ .virt_start = 0x0f140000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* sai6 */ {
+ .phys_start = 0x0f150000,
+ .virt_start = 0x0f150000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* tmu */ {
+ .phys_start = 0x01f80000,
+ .virt_start = 0x01f80000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie */ {
+ .phys_start = 0x1f0000000,
+ .virt_start = 0x1f0000000,
+ .size = 0x10000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pwm0 */ {
+ .phys_start = 0x02800000,
+ .virt_start = 0x02800000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pwm1 */ {
+ .phys_start = 0x02810000,
+ .virt_start = 0x02810000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pwm2 */ {
+ .phys_start = 0x02820000,
+ .virt_start = 0x02820000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pwm3 */ {
+ .phys_start = 0x02830000,
+ .virt_start = 0x02830000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pwm4 */ {
+ .phys_start = 0x02840000,
+ .virt_start = 0x02840000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pwm5 */ {
+ .phys_start = 0x02850000,
+ .virt_start = 0x02850000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pwm6 */ {
+ .phys_start = 0x02860000,
+ .virt_start = 0x02860000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pwm7 */ {
+ .phys_start = 0x02870000,
+ .virt_start = 0x02870000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* rcpm */ {
+ .phys_start = 0x01e30000,
+ .virt_start = 0x01e30000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* dpclk */ {
+ .phys_start = 0x0f1f0000,
+ .virt_start = 0x0f1f0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* malidp */ {
+ .phys_start = 0x0f080000,
+ .virt_start = 0x0f080000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* hdptx0 */ {
+ .phys_start = 0x0f200000,
+ .virt_start = 0x0f200000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */ {
+ .address = 0x6000000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+ },
+ },
+ /* GIC */ {
+ .address = 0x6000000,
+ .pin_base = 160,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+ },
+ },
+ },
+
+ .pci_devices = {
+ { /* IVSHMEM 00:00.0 */
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 0,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 0,
+ .shmem_peers = 2,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ { /* IVSHMEM 00:01.0 */
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 0,
+ .bdf = 1 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 4,
+ .shmem_dev_id = 0,
+ .shmem_peers = 2,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
+ },
+ },
+};
--
2.17.1
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