Hi there,
Our target is Sitara AM5726 , CortexA15 dual core on which we are running Linux on A15 core0 and RTOS on core1. RTOS gets periodic interrupt from external hardware via nirq1 pin (dedicated input into ARM gic). Under heavy load in Linux (core 0!), RTOS, which runs on core1 misses interrupts. Questions 1. Does linux/hypervisor participate in interrupt scheduling/forwarding to cell on Core1 2. Is there a description of interrupt forwarding/virtualization scheme to cores (if exists)? Any pointer to document/source code would be appreciated. Thanks a lot, Nir. -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/fde55f66-2e83-4df2-8f5e-44b0fb831acbn%40googlegroups.com.
