> Subject: Re: str wzr, [x1, #16]! triggers EL2 unhandled data abort
> 
> Hi Peng,
> 
> Am 12.12.23 um 08:52 schrieb Peng Fan:
> > Hi Alex,
> >
> >> Subject: Re: str wzr, [x1, #16]! triggers EL2 unhandled data abort
> >>
> >> Hi Peng,
> >>
> >> Am 12.12.23 um 03:42 schrieb Peng Fan:
> >>> Hi All,
> >>>
> >>>
> >>> I am running jailhouse on i.MX9 Cortex-A55, and meet an issue.
> >>> " str     wzr, [x1, #16]! " this instruction in EL0 triggers unhanlded
> >>> Data abort in EL2, with ISS is data abort, ISV is 0.
> >>>
> >>> I am not sure why this instruction trigger DC with ISV 0.
> >>> Any ideas are appreciated.
> >>>
> >>> Thanks,
> >>> Peng.
> >>
> >> The Arm architecture cannot provide all information in ISS for
> >> instructions that also update the base register.
> >
> > Does ARM architecture TRM note this? Would you please share me the
> > Chapter?
> 
> In my old version of the Arm ARM it's noted in Section D7.2.27 "ESR_ELx,
> Exception Syndrome Register (ELx)" in the description of the ISV bit:
> > Instruction syndrome valid ...
> > This bit is 0 for all faults reported in ESR_EL2 except the following
> > stage 2
> aborts:
> > • AArch64 loads and stores ... and excluding those with writeback.
> 
> 
> >> You need to change the code sequence to:
> >>   str     wzr, [x1, #16]
> >>   add     x1, x1, #16
> >
> > Hmm, but gcc generates "str wzr, [x1, #16]!" from c code.
> >
> > This should be common issue I think.
> 
> Yes, and I remember that there was some discussion on this on the LKML
> years ago. The raw accessors in Linux like __raw_writel() enforce the simple
> load/store forms to aid virtualization-

Thanks very much, I will try this.

Thanks,
Peng.

> 
> Best regards
> Alex
> 
> 
> >
> > Thanks,
> > Peng.
> >
> >>
> >>
> >> Best regards
> >> Alex

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