Hi Joep,
Joep Suijs wrote: > .... > This is why the shadow register is introduced. It contains the value > that all pins of a port should be driven to when they are on output. > It is important that this register is never 'contaminated' with values > acually read from the port (and it is also important that the shadow > register is updated by all changes in desired port values - bit, > nibble and byte). Thanks for the explanation. In the meantime I have also been (re-)reading some of the many articles about this issue! Will I ever understand it completely? I doubt it and I'm afraid I'm not the only one! But once it is handled correctly in the device files no Jallib user has ever to bother about it. I got confused this time by thinking that writing the shadow registers might influence pins which are set for input. [about the 18Fs] > PPS I saw this code: > var volatile bit LATB_LATB5 shared at LATB : 5 > var volatile bit pin_B5 shared at PORTB : 5 > procedure pin_B5'put(bit in x at LATB : 5) is > pragma inline > end procedure > > Does this mean that LATB is actually an output-only register so there > is no such thing as an RMW problem on 18f chips? AKAIK LAT registers are read/write. With the declaration above: when you write to pin_B5 the 'put routine is called and LATB:5 is set, and when you read pin_B5 you get the value of LATB:5. Albert suggested to return the value of PORTB:5. So pins would be better declared as: var volatile bit pin_B5 shared at PORTB : 5 (no changes in the 'put procedure). The nibble declaration needs a similar change. Regards. Rob -- Rob Hamerling, Vianen, NL (http://www.robh.nl/) --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/jallib?hl=en -~----------~----~----~----~------~----~------~--~---
