Revision: 1647
Author: robhamerling
Date: Mon Feb 1 12:23:07 2010
Log: Update of devicefiles.html w.r.t. naming convention for USART registers
http://code.google.com/p/jallib/source/detail?r=1647
Modified:
/trunk/doc/html/devicefiles.html
=======================================
--- /trunk/doc/html/devicefiles.html Wed Dec 9 01:12:24 2009
+++ /trunk/doc/html/devicefiles.html Mon Feb 1 12:23:07 2010
@@ -581,6 +581,58 @@
'binary' field, regardless if the bits are scattered over the register or
not.
+<h3>Names of registers and subfields of [E]USART modules</h3>
+<p>PICs can have zero, one or two USART modules, of which zero, one or both
+can be 'extended' (EUSART) modules.
+Compared to a 'legacy' USART an 'extended' USART has a BAUDCON
+register and can use a 16 bits in stead of an 8-bits value for the
+baudrate divisor,
+allowing a more accurate baudrate setting, especially at high speeds.
+<p>The names of USART related registers and -subfields are not particular
+constent in the MPLAB .dev files, so it is desired to normalize these.
+And it would be convenient if serial libraries supporting a single serial
+interface could be used one of both USARTs of PICs with two USARTs.
+These are the primary reasons for the following naming convention in the
+Jallib device files:
+<ul>
+<li>for PICs with 1 USART:
+ <ul>
+ <li>no suffix
+ </ul>
+<li>for PICS with 2 USARTs:
+ <ul>
+ <li>first USART: suffix '1' and an alias without suffix
+ <li>second USART: suffix '2'
+ </ul>
+</ul>
+<p>Application of these rules results in the following list of names:
+<table>
+<tr><th>single USART <th>first of 2 USARTs <th>second of 2
USARTs</tr>
+<tr><td>BAUDCON <td>BAUDCON1<br>BAUDCON (alias) <td>BAUDCON2
</tr>
+<tr><td>BAUDCTL <td>BAUDCTL1<br>BAUDCTL (alias) <td>BAUDCTL2
</tr>
+<tr><td>RCREG <td>RCREG1<br>RCREG (alias) <td>RCREG2
</tr>
+<tr><td>RCSTA <td>RCSTA1<br>RCSTA (alias) <td>RCSTA2
</tr>
+<tr><td>SPBRG <td>SPBRG1<br>SPBRG (alias) <td>SPBRG2
</tr>
+<tr><td>SPBRGH <td>SPBRGH1<br>SPBRGH (alias) <td>SPBRGH2
</tr>
+<tr><td>TXREG <td>TXREG1<br>TXREG (alias) <td>TXREG2
</tr>
+<tr><td>TXSTA <td>TXSTA1<br>TXSTA (alias) <td>TXSTA2
</tr>
+<tr><td>PIE1_RCIE <td>PIE1_RC1IE<br>PIE1_RCIE (alias) <td>PIE3_RC2IE
</tr>
+<tr><td>PIE1_TXIE <td>PIE1_TX1IE<br>PIE1_TXIE (alias) <td>PIE3_TX2IE
</tr>
+<tr><td>PIR1_RCIF <td>PIR1_RC1IF<br>PIR1_RCIF (alias) <td>PIR3_RC2IF
</tr>
+<tr><td>PIR1_TXIF <td>PIR1_TX1IF<br>PIR1_TXIF (alias) <td>PIR3_TX2IF
</tr>
+</table>
+<p>Notes:
+<ul compact>
+<li>BAUDCON and SPBGRH registers are only available with extended USARTs.
+<li>The original name and the alias might appear exchanged.
+</ul>
+<p>With these names serial libaries or application programs supporting only
+a single serial interface can use the register and field names without
+suffix for the only USART or the first of two USARTs.
+Libraries supporting two serial interfaces will preferrably use the
+qualified names (with suffix).
+
+
<h3>Names of Timer fields</h3>
<p>Some register subfields of timer control registers have inconsistent
names in the MPLAB .dev files.
@@ -961,6 +1013,9 @@
EC_NOCLKOUT -- External Clock (TTL) signal on OSC1, OSC2 is I/O
EC_CLKOUT_PLL -- EC_CLKOUT with PLL active
EC_NOCLKOUT_PLL -- EC_NOCLKOUT with PLL active
+ ECH_NOCLKOUT -- external clock, high power mode
+ ECL_NOCLKOUT -- external clock, low power mode
+ ECM_NOCLKOUT -- external clock, medium power mode
RC_CLKOUT -- (external) Resistor/Capacitor oscillator on OSC1,
ClockOut on OSC2
RC_NOCLKOUT -- (external) Resistor/Capacitor oscillator on OSC1,
OSC2 is I/O
INTOSC_CLKOUT -- Internal oscillator, OSC1 is I/O, ClockOut on OSC2
--
You received this message because you are subscribed to the Google Groups
"jallib" group.
To post to this group, send email to [email protected].
To unsubscribe from this group, send email to
[email protected].
For more options, visit this group at
http://groups.google.com/group/jallib?hl=en.
