Hi Joep, As I understand the problem: some registers as hardware RTCC or Peripheral Pin Select Register (PPS) need the "magic Microchip sequence" meaning a writing of 0x55 followed by 0xAA into the EECON register. All good so far, but previously to writing that sequence the compiler must be in the same bank for which register is written that sequence (bank 15 for RTCC or bank 14 for PPS). Because there is no user available assembler instruction for "movlb", this must be solved either by asm bank register or a jal pseudo-write in that register used only to change the bank (see example B below).
Vasile On Tue, Jul 27, 2010 at 2:05 PM, Joep Suijs <[email protected]> wrote: > Hi all, > > Could someone please explain what the purpose is of 'asm bank RTCCFG' > and why it is required? My assumption (until now) was that JAL handles > all banking as long as you don't use assembler. > > Joep > > 2010/7/27 vasile surducan <[email protected]>: > > > > Two different procedures with the same result: > > A: > > -- ---------------------------------------------------------------------- > > -- Enable RTCC register writes > > -- input: bit (enable / disable) > > -- output: none > > -- returns: nothing > > -- notes: Setting the RTCWREN bit in RTCCFG requires a strict > > -- sequence, some assembly language need to be used. > > -- ---------------------------------------------------------------------- > > procedure _rtc_write_control(bit in control) is > > asm bank RTCCFG -- set bank of RTCCFG > > if (control == enabled) then > > EECON2 = 0x55 -- ) write .. > > EECON2 = 0xAA -- ) .. enable > > RTCCFG_RTCWREN = enabled -- allow writes > > else > > EECON2 = 0x55 -- ) write .. > > EECON2 = 0xAA -- ) .. enable > > RTCCFG_RTCWREN = disabled -- deny writes > > end if > > end procedure > > > > B: > > -- ---------------------------------------------------------------------- > > -- Enable RTCC register writes > > -- input: bit (RTC_enabled / RTC_disabled) > > -- ---------------------------------------------------------------------- > > const bit RTC_enabled = 1 > > const bit RTC_disabled = 0 > > procedure RTC_writing (bit in value) is > > asm bank RTCCFG ; identical with RTCCFG_RTCWREN = value used only to set > > bank 15 > > EECON2 = 0x55 -- \ required sequence > > EECON2 = 0xAA -- / > > RTCCFG_RTCWREN = value ; enable/disable writting to RTCCFG > > end procedure > > > > -- > > You received this message because you are subscribed to the Google Groups > > "jallib" group. > > To post to this group, send email to [email protected]. > > To unsubscribe from this group, send email to > > [email protected]<jallib%[email protected]> > . > > For more options, visit this group at > > http://groups.google.com/group/jallib?hl=en. > > > > -- > You received this message because you are subscribed to the Google Groups > "jallib" group. > To post to this group, send email to [email protected]. > To unsubscribe from this group, send email to > [email protected]<jallib%[email protected]> > . > For more options, visit this group at > http://groups.google.com/group/jallib?hl=en. > > -- You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/jallib?hl=en.
