Hi Vasile,

I'm afraid I don't understand what change you suggest, but it is
probably related to board files. Could you please indicate which
device sample you suggest to be changed and how it should look?
I guess the eeprom stuff is okay ;)

Joep

2012/4/30 vasile surducan <[email protected]>:
> Hi Joep,
>
> I suggest the following modification to all PLL based microcontrollers
> samples:
>
> -- even though the external crystal is 20 MHz, the configuration is such
> that
> -- the CPU clock is derived from the 96 Mhz PLL clock (div2), therefore set
> -- target frequency to 48 MHz if pragma target CPUDIV is P1
>
> instead of:
> -- even though the external crystal is 20 MHz, the configuration is such
> that
> -- the CPU clock is derived from the 96 Mhz PLL clock (div2), therefore set
> -- target frequency to 48 MHz
>
> Pragma target clock is dependant by pragma target CPUDIV.
>
> Vasile
>
>
> On Sun, Apr 29, 2012 at 9:14 PM, <[email protected]> wrote:
>>
>> Revision: 3053
>> Author:   jsuijs
>> Date:     Sun Apr 29 11:14:24 2012
>> Log:      The samples for the new 24lc256 lib
>> http://code.google.com/p/jallib/source/detail?r=3053
>>
>> Added:
>>  /trunk/sample/16f648a_24lc256_II.jal
>>  /trunk/sample/16f723_24lc256_II.jal
>>  /trunk/sample/16f877_24lc256_II.jal
>>  /trunk/sample/16f877a_24lc256_II.jal
>>  /trunk/sample/16f88_24lc256_II.jal
>>  /trunk/sample/18f14k50_24lc256_II.jal
>>  /trunk/sample/18f2450_24lc256_II.jal
>>  /trunk/sample/18f2620_24lc256_II.jal
>>  /trunk/sample/18f4550_24lc256_II.jal
>>  /trunk/test/external/test_24lc256_II.jal
>> Deleted:
>>  /trunk/test/external/test_24lc256.jal
>> Modified:
>>  /trunk/sample/18f2620_i2c_hw_l0.jal
>>  /trunk/sample/18f2620_i2c_hw_l1.jal
>>  /trunk/sample/18f2620_i2c_sw_l0.jal
>>  /trunk/sample/18f2620_i2c_sw_l1.jal
>>  /trunk/sample/18f2620_i2c_sw_master_check_bus.jal
>>  /trunk/sample/18f2620_i2c_sw_master_echo.jal
>>  /trunk/sample/18f2620_lcd_dsm0822a.jal
>>  /trunk/sample/18f2620_lcd_hd44780_pcf8574.jal
>>  /trunk/test/board/board_18f2620_js.jal
>>
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