Hi,

Hope you are doing great. Please go through the requirement and send me best
match open for this position

Title: FPGA Design Validation Engineer
Location: Chandler. AZ
Duration: 6 month(s)

Years of Experience & Expertise Level: (Allow us to recruit for the best
possible skill level, i.e. Jr, Mid or Sr.) 8-10 years and senior engineer

Project Description: 
PCIe based FPGA platform design and verification

Daily Responsibilities: 
Develop FPGA RTL and validate the design in simulation and FPGA platform in
lab

Necessary Skills (Must Have): 
• A BS in Electrical Engineering, 7-10 years industry experience and at
least 5 years FPGA development experience. The candidate must possess: 
• An expert working knowledge of design and analysis of digital logic
• Expert Knowledge design and verification using Verilog and System Verilog
• Experience on PCIe design and validation
• Expert working knowledge of VCS, Synplify Pro* synthesis tool, Identify,
Xilinx* ISE tool, Xilinx Virtex-5
• A self starter who can work with minimal supervision in a team environment
• Solid lab skills, including (but not limited to) experience with digital
multi-meters, digital storage oscilloscopes, logic analyzers, function
generators, digital stimulus generators, frequency counters, and power
supplies
• Tcl/tk scripting experience and/or shell* programming would be an added
advantage

Additional Skills Desired (Nice to Have):
• Experience of OVM based SystemVerilog validation environment.
• Experience on Synopsys HAPS FPGA platform.


Regards,
Monty Singh
Technical Recruiter
 
Ask IT Consulting
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Phone: 516-717-2047
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Email: [email protected] 
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