*Role: ASIC Physical Design Engineer* *Duration: 3 to 6 months (extension possible)*
*Location: Hillsboro, OR* *Job Description * *Qualifications Basic* · Bachelor’s degree or foreign equivalent required. · 4 to 6 years of experience in ASIC Physical Design *Preferred Expertise* · At least 4 years of experience in the following skills - Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verification(DRC, LVS) and Power Analysis(IR drop, EMIG), Leakage Power Optimization using ICCLR/PTLR flows, on 22nm, 14nm, or lower process technology · Desired Tools Experience: Synopsys ICC flow, Prime Time, Design Compiler, Redhawk, LEC/Formality, and Caliber. · At least 4 years of experience in Project life cycle activities on development and maintenance projects. · At least 4 years of experience in Physical Design and STA review. · At least 4 years of experience in ASIC development life cycle. · Ability to work in team in diverse/ multiple stakeholder environment -- You received this message because you are subscribed to the Google Groups "Jenkins Issues" group. To unsubscribe from this group and stop receiving emails from it, send an email to jenkinsci-issues+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
