Thanks, Richard. 2010/8/29 Richard A Steenbergen <r...@e-gerbil.net>
> > * Each Trio PFE is composed of the following ASICs: > > - MQ: Handles the packet memory, talks to the chassis fabric and the > WAN ports, handles port-based QoS, punts first part of the packet > to the LU chip for routing lookups. > - LU: Lookup ASIC which does all IP routing lookups, MAC lookups, > label switching, firewall matching, policing, accounting, etc. > - QX: (optional) Implements the fine grained queueing/HQoS stuff. > NOT included on the 16-port 10GE MPC. > - IX: (optional) Sits in front of the MQ chip to handle GigE ports. > Here is another joke about '3D' name pronounced by Juniper's people: it's called 3D because it actually consists of four chips. > * The Trio PFE is good for around 55Mpps of lookups, give or take, > depending on the exact operations being performed. > 55, not 65? Anyway, this is what I can't understand (maybe because of my not-native English). When you say 'give or take', you mean it can only do 55/65 for both directions or 55/65 for ethernet->backplane and 55/65 backwards? If this is an LU overall limit for both direction than either I can't manage to convert pps to bps (65pps is about 30 Gigs for 64-byte packets, isn't it) or everything has is twice less performance than we think (not likely though). -- Pavel _______________________________________________ juniper-nsp mailing list juniper-nsp@puck.nether.net https://puck.nether.net/mailman/listinfo/juniper-nsp