CC: kbuild-...@lists.01.org BCC: l...@intel.com TO: Srikanth Thokala <srikanth.thok...@intel.com> CC: nanli2x <nanx...@intel.com>
tree: https://github.com/intel/linux-intel-lts.git 5.15/linux head: 7acd0be121091f12349a4dcefd2e6deee2e73946 commit: 28f72667fffb64d777e6f3f3017995d7d4f9e558 [4/5] PCI: thunderbay: Add support for Thunderbay Root Port :::::: branch date: 4 days ago :::::: commit date: 9 weeks ago config: xtensa-randconfig-m031-20220422 (https://download.01.org/0day-ci/archive/20220423/202204232110.scxhvyg9-...@intel.com/config) compiler: xtensa-linux-gcc (GCC) 11.2.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <l...@intel.com> Reported-by: Dan Carpenter <dan.carpen...@oracle.com> New smatch warnings: drivers/pci/controller/dwc/pcie-keembay.c:255 thunderbay_pcie_host_rd_other_conf() error: uninitialized symbol 'ret'. drivers/pci/controller/dwc/pcie-keembay.c:294 thunderbay_pcie_rc_dma_cfg() warn: passing zero to 'PTR_ERR' Old smatch warnings: drivers/pci/controller/dwc/pcie-keembay.c:301 thunderbay_pcie_rc_dma_cfg() warn: passing zero to 'PTR_ERR' vim +/ret +255 drivers/pci/controller/dwc/pcie-keembay.c 28f72667fffb64 Srikanth Thokala 2021-09-16 219 28f72667fffb64 Srikanth Thokala 2021-09-16 220 static int 28f72667fffb64 Srikanth Thokala 2021-09-16 221 thunderbay_pcie_host_rd_other_conf(struct pci_bus *bus, unsigned int devfn, 28f72667fffb64 Srikanth Thokala 2021-09-16 222 int where, int size, u32 *val) 28f72667fffb64 Srikanth Thokala 2021-09-16 223 { 28f72667fffb64 Srikanth Thokala 2021-09-16 224 struct pcie_port *pp = bus->sysdata; 28f72667fffb64 Srikanth Thokala 2021-09-16 225 struct keembay_pcie *pcie; 28f72667fffb64 Srikanth Thokala 2021-09-16 226 int ret, where_align; 28f72667fffb64 Srikanth Thokala 2021-09-16 227 struct dw_pcie *pci; 28f72667fffb64 Srikanth Thokala 2021-09-16 228 28f72667fffb64 Srikanth Thokala 2021-09-16 229 pci = to_dw_pcie_from_pp(pp); 28f72667fffb64 Srikanth Thokala 2021-09-16 230 pcie = dev_get_drvdata(pci->dev); 28f72667fffb64 Srikanth Thokala 2021-09-16 231 28f72667fffb64 Srikanth Thokala 2021-09-16 232 if (pcie->rc_dma) { 28f72667fffb64 Srikanth Thokala 2021-09-16 233 where_align = where & ~((typeof(where))(4) - 1); 28f72667fffb64 Srikanth Thokala 2021-09-16 234 if (thunderbay_pcie_rc_dma_rd(pp, 28f72667fffb64 Srikanth Thokala 2021-09-16 235 pcie->rd_dma_chan, 28f72667fffb64 Srikanth Thokala 2021-09-16 236 pcie->rc_dma_mem_pa + where_align, 28f72667fffb64 Srikanth Thokala 2021-09-16 237 pp->cfg0_base + where_align, 28f72667fffb64 Srikanth Thokala 2021-09-16 238 4)) 28f72667fffb64 Srikanth Thokala 2021-09-16 239 ret = PCIBIOS_BAD_REGISTER_NUMBER; 28f72667fffb64 Srikanth Thokala 2021-09-16 240 28f72667fffb64 Srikanth Thokala 2021-09-16 241 *val = *((int *)(pcie->rc_dma_mem_va + where)); 28f72667fffb64 Srikanth Thokala 2021-09-16 242 28f72667fffb64 Srikanth Thokala 2021-09-16 243 if (size == 4) 28f72667fffb64 Srikanth Thokala 2021-09-16 244 *val &= 0xFFFFFFFF; 28f72667fffb64 Srikanth Thokala 2021-09-16 245 else if (size == 2) 28f72667fffb64 Srikanth Thokala 2021-09-16 246 *val &= 0xFFFF; 28f72667fffb64 Srikanth Thokala 2021-09-16 247 else if (size == 1) 28f72667fffb64 Srikanth Thokala 2021-09-16 248 *val &= 0xFF; 28f72667fffb64 Srikanth Thokala 2021-09-16 249 else 28f72667fffb64 Srikanth Thokala 2021-09-16 250 ret = PCIBIOS_BAD_REGISTER_NUMBER; 28f72667fffb64 Srikanth Thokala 2021-09-16 251 } else { 28f72667fffb64 Srikanth Thokala 2021-09-16 252 ret = dw_pcie_read(pp->va_cfg0_base + where, size, val); 28f72667fffb64 Srikanth Thokala 2021-09-16 253 } 28f72667fffb64 Srikanth Thokala 2021-09-16 254 28f72667fffb64 Srikanth Thokala 2021-09-16 @255 return ret; 28f72667fffb64 Srikanth Thokala 2021-09-16 256 } 28f72667fffb64 Srikanth Thokala 2021-09-16 257 28f72667fffb64 Srikanth Thokala 2021-09-16 258 static struct pci_ops thunderbay_child_pci_ops = { 28f72667fffb64 Srikanth Thokala 2021-09-16 259 .map_bus = thunderbay_pcie_conf_addr_map_bus, 28f72667fffb64 Srikanth Thokala 2021-09-16 260 .read = thunderbay_pcie_host_rd_other_conf, 28f72667fffb64 Srikanth Thokala 2021-09-16 261 .write = pci_generic_config_write, 28f72667fffb64 Srikanth Thokala 2021-09-16 262 }; 28f72667fffb64 Srikanth Thokala 2021-09-16 263 28f72667fffb64 Srikanth Thokala 2021-09-16 264 static int thunderbay_pcie_rc_dma_cfg(struct keembay_pcie *pcie, 28f72667fffb64 Srikanth Thokala 2021-09-16 265 struct platform_device *pdev) 28f72667fffb64 Srikanth Thokala 2021-09-16 266 { 28f72667fffb64 Srikanth Thokala 2021-09-16 267 struct dw_pcie *pci = &pcie->pci; 28f72667fffb64 Srikanth Thokala 2021-09-16 268 struct device *dev = &pdev->dev; 28f72667fffb64 Srikanth Thokala 2021-09-16 269 struct dma_chan *rd_chan; 28f72667fffb64 Srikanth Thokala 2021-09-16 270 dma_addr_t phys; 28f72667fffb64 Srikanth Thokala 2021-09-16 271 void *segment; 28f72667fffb64 Srikanth Thokala 2021-09-16 272 int ret; 28f72667fffb64 Srikanth Thokala 2021-09-16 273 28f72667fffb64 Srikanth Thokala 2021-09-16 274 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 28f72667fffb64 Srikanth Thokala 2021-09-16 275 if (ret) 28f72667fffb64 Srikanth Thokala 2021-09-16 276 dev_warn(dev, "failed to set dma mask\n"); 28f72667fffb64 Srikanth Thokala 2021-09-16 277 28f72667fffb64 Srikanth Thokala 2021-09-16 278 rd_chan = dma_request_chan(&pdev->dev, "rx"); 28f72667fffb64 Srikanth Thokala 2021-09-16 279 if (IS_ERR(rd_chan)) { 28f72667fffb64 Srikanth Thokala 2021-09-16 280 ret = PTR_ERR(rd_chan); 28f72667fffb64 Srikanth Thokala 2021-09-16 281 if (ret != -EPROBE_DEFER) 28f72667fffb64 Srikanth Thokala 2021-09-16 282 dev_err(dev, "No RC AXI DMA Rd channel available\n"); 28f72667fffb64 Srikanth Thokala 2021-09-16 283 return ret; 28f72667fffb64 Srikanth Thokala 2021-09-16 284 } 28f72667fffb64 Srikanth Thokala 2021-09-16 285 pcie->rd_dma_chan = rd_chan; 28f72667fffb64 Srikanth Thokala 2021-09-16 286 28f72667fffb64 Srikanth Thokala 2021-09-16 287 pcie->rc_dma_pool = dma_pool_create("thb_pcie_rc_dma_pool", 28f72667fffb64 Srikanth Thokala 2021-09-16 288 pci->dev, 28f72667fffb64 Srikanth Thokala 2021-09-16 289 PAGE_SIZE, 28f72667fffb64 Srikanth Thokala 2021-09-16 290 PAGE_SIZE, 28f72667fffb64 Srikanth Thokala 2021-09-16 291 0); 28f72667fffb64 Srikanth Thokala 2021-09-16 292 if (!pcie->rc_dma_pool) { 28f72667fffb64 Srikanth Thokala 2021-09-16 293 dev_err(dev, "unable to allocate RC AXI DMA pool\n"); 28f72667fffb64 Srikanth Thokala 2021-09-16 @294 ret = PTR_ERR(pcie->rc_dma_pool); 28f72667fffb64 Srikanth Thokala 2021-09-16 295 goto free_dma_channel; 28f72667fffb64 Srikanth Thokala 2021-09-16 296 } 28f72667fffb64 Srikanth Thokala 2021-09-16 297 28f72667fffb64 Srikanth Thokala 2021-09-16 298 segment = dma_pool_zalloc(pcie->rc_dma_pool, GFP_ATOMIC, &phys); 28f72667fffb64 Srikanth Thokala 2021-09-16 299 if (!segment) { 28f72667fffb64 Srikanth Thokala 2021-09-16 300 dev_err(dev, "unable to get mem from RC AXI DMA pool\n"); 28f72667fffb64 Srikanth Thokala 2021-09-16 301 ret = PTR_ERR(segment); 28f72667fffb64 Srikanth Thokala 2021-09-16 302 goto free_dma_pool; 28f72667fffb64 Srikanth Thokala 2021-09-16 303 } 28f72667fffb64 Srikanth Thokala 2021-09-16 304 pcie->rc_dma_mem_pa = phys; 28f72667fffb64 Srikanth Thokala 2021-09-16 305 pcie->rc_dma_mem_va = segment; 28f72667fffb64 Srikanth Thokala 2021-09-16 306 28f72667fffb64 Srikanth Thokala 2021-09-16 307 return 0; 28f72667fffb64 Srikanth Thokala 2021-09-16 308 28f72667fffb64 Srikanth Thokala 2021-09-16 309 free_dma_channel: 28f72667fffb64 Srikanth Thokala 2021-09-16 310 dma_release_channel(pcie->rd_dma_chan); 28f72667fffb64 Srikanth Thokala 2021-09-16 311 free_dma_pool: 28f72667fffb64 Srikanth Thokala 2021-09-16 312 dma_pool_destroy(pcie->rc_dma_pool); 28f72667fffb64 Srikanth Thokala 2021-09-16 313 28f72667fffb64 Srikanth Thokala 2021-09-16 314 return ret; 28f72667fffb64 Srikanth Thokala 2021-09-16 315 } 28f72667fffb64 Srikanth Thokala 2021-09-16 316 -- 0-DAY CI Kernel Test Service https://01.org/lkp _______________________________________________ kbuild mailing list -- kbuild@lists.01.org To unsubscribe send an email to kbuild-le...@lists.01.org
