CC: kbuild-...@lists.01.org BCC: l...@intel.com CC: Alison Schofield <alison.schofi...@intel.com> CC: Vishal Verma <vishal.l.ve...@intel.com> CC: Ira Weiny <ira.we...@intel.com> CC: Ben Widawsky <ben.widaw...@intel.com> CC: Dan Williams <dan.j.willi...@intel.com> TO: Dan Williams <dan.j.willi...@intel.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git preview head: b282b26d11c50d48b336fedb5f74b2eca3f7b94c commit: 60123aa889a00573086429b55cc7f94ab157fbb4 [55/59] cxl/region: Program target lists :::::: branch date: 3 days ago :::::: commit date: 3 days ago config: riscv-randconfig-m041-20220722 (https://download.01.org/0day-ci/archive/20220724/202207242005.ac7gjm4h-...@intel.com/config) compiler: riscv64-linux-gcc (GCC) 12.1.0 If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot <l...@intel.com> Reported-by: Dan Carpenter <dan.carpen...@oracle.com> New smatch warnings: drivers/cxl/core/region.c:833 cxl_port_setup_targets() error: uninitialized symbol 'peig'. drivers/cxl/core/region.c:833 cxl_port_setup_targets() error: uninitialized symbol 'peiw'. drivers/cxl/core/region.c:833 cxl_port_setup_targets() error: uninitialized symbol 'eiw'. Old smatch warnings: drivers/cxl/core/region.c:290 alloc_hpa() error: uninitialized symbol 'res'. drivers/cxl/core/region.c:837 cxl_port_setup_targets() error: uninitialized symbol 'peiw'. drivers/cxl/core/region.c:838 cxl_port_setup_targets() error: uninitialized symbol 'peig'. drivers/cxl/core/region.c:1410 create_pmem_region_store() warn: unsigned 'rc' is never less than zero. vim +/peig +833 drivers/cxl/core/region.c 60123aa889a005 Dan Williams 2022-06-06 764 60123aa889a005 Dan Williams 2022-06-06 765 static int cxl_port_setup_targets(struct cxl_port *port, 60123aa889a005 Dan Williams 2022-06-06 766 struct cxl_region *cxlr, 60123aa889a005 Dan Williams 2022-06-06 767 struct cxl_endpoint_decoder *cxled) 60123aa889a005 Dan Williams 2022-06-06 768 { 60123aa889a005 Dan Williams 2022-06-06 769 struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent); 60123aa889a005 Dan Williams 2022-06-06 770 int parent_iw, parent_ig, ig, iw, rc, inc = 0, pos = cxled->pos; 60123aa889a005 Dan Williams 2022-06-06 771 struct cxl_port *parent_port = to_cxl_port(port->dev.parent); 60123aa889a005 Dan Williams 2022-06-06 772 struct cxl_region_ref *cxl_rr = cxl_rr_load(port, cxlr); 60123aa889a005 Dan Williams 2022-06-06 773 struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); 60123aa889a005 Dan Williams 2022-06-06 774 struct cxl_ep *ep = cxl_ep_load(port, cxlmd); 60123aa889a005 Dan Williams 2022-06-06 775 struct cxl_region_params *p = &cxlr->params; 60123aa889a005 Dan Williams 2022-06-06 776 struct cxl_decoder *cxld = cxl_rr->decoder; 60123aa889a005 Dan Williams 2022-06-06 777 struct cxl_switch_decoder *cxlsd; 60123aa889a005 Dan Williams 2022-06-06 778 u16 eig, peig; 60123aa889a005 Dan Williams 2022-06-06 779 u8 eiw, peiw; 60123aa889a005 Dan Williams 2022-06-06 780 60123aa889a005 Dan Williams 2022-06-06 781 /* 60123aa889a005 Dan Williams 2022-06-06 782 * While root level decoders support x3, x6, x12, switch level 60123aa889a005 Dan Williams 2022-06-06 783 * decoders only support powers of 2 up to x16. 60123aa889a005 Dan Williams 2022-06-06 784 */ 60123aa889a005 Dan Williams 2022-06-06 785 if (!is_power_of_2(cxl_rr->nr_targets)) { 60123aa889a005 Dan Williams 2022-06-06 786 dev_dbg(&cxlr->dev, "%s:%s: invalid target count %d\n", 60123aa889a005 Dan Williams 2022-06-06 787 dev_name(port->uport), dev_name(&port->dev), 60123aa889a005 Dan Williams 2022-06-06 788 cxl_rr->nr_targets); 60123aa889a005 Dan Williams 2022-06-06 789 return -EINVAL; 60123aa889a005 Dan Williams 2022-06-06 790 } 60123aa889a005 Dan Williams 2022-06-06 791 60123aa889a005 Dan Williams 2022-06-06 792 cxlsd = to_cxl_switch_decoder(&cxld->dev); 60123aa889a005 Dan Williams 2022-06-06 793 if (cxl_rr->nr_targets_set) { 60123aa889a005 Dan Williams 2022-06-06 794 int i, distance; 60123aa889a005 Dan Williams 2022-06-06 795 60123aa889a005 Dan Williams 2022-06-06 796 distance = p->nr_targets / cxl_rr->nr_targets; 60123aa889a005 Dan Williams 2022-06-06 797 for (i = 0; i < cxl_rr->nr_targets_set; i++) 60123aa889a005 Dan Williams 2022-06-06 798 if (ep->dport == cxlsd->target[i]) { 60123aa889a005 Dan Williams 2022-06-06 799 rc = check_last_peer(cxled, ep, cxl_rr, 60123aa889a005 Dan Williams 2022-06-06 800 distance); 60123aa889a005 Dan Williams 2022-06-06 801 if (rc) 60123aa889a005 Dan Williams 2022-06-06 802 return rc; 60123aa889a005 Dan Williams 2022-06-06 803 goto out_target_set; 60123aa889a005 Dan Williams 2022-06-06 804 } 60123aa889a005 Dan Williams 2022-06-06 805 goto add_target; 60123aa889a005 Dan Williams 2022-06-06 806 } 60123aa889a005 Dan Williams 2022-06-06 807 60123aa889a005 Dan Williams 2022-06-06 808 if (is_cxl_root(parent_port)) { 60123aa889a005 Dan Williams 2022-06-06 809 parent_ig = cxlrd->cxlsd.cxld.interleave_granularity; 60123aa889a005 Dan Williams 2022-06-06 810 parent_iw = cxlrd->cxlsd.cxld.interleave_ways; 60123aa889a005 Dan Williams 2022-06-06 811 /* 60123aa889a005 Dan Williams 2022-06-06 812 * For purposes of address bit routing, use power-of-2 math for 60123aa889a005 Dan Williams 2022-06-06 813 * switch ports. 60123aa889a005 Dan Williams 2022-06-06 814 */ 60123aa889a005 Dan Williams 2022-06-06 815 if (!is_power_of_2(parent_iw)) 60123aa889a005 Dan Williams 2022-06-06 816 parent_iw /= 3; 60123aa889a005 Dan Williams 2022-06-06 817 } else { 60123aa889a005 Dan Williams 2022-06-06 818 struct cxl_region_ref *parent_rr; 60123aa889a005 Dan Williams 2022-06-06 819 struct cxl_decoder *parent_cxld; 60123aa889a005 Dan Williams 2022-06-06 820 60123aa889a005 Dan Williams 2022-06-06 821 parent_rr = cxl_rr_load(parent_port, cxlr); 60123aa889a005 Dan Williams 2022-06-06 822 parent_cxld = parent_rr->decoder; 60123aa889a005 Dan Williams 2022-06-06 823 parent_ig = parent_cxld->interleave_granularity; 60123aa889a005 Dan Williams 2022-06-06 824 parent_iw = parent_cxld->interleave_ways; 60123aa889a005 Dan Williams 2022-06-06 825 } 60123aa889a005 Dan Williams 2022-06-06 826 60123aa889a005 Dan Williams 2022-06-06 827 granularity_to_cxl(parent_ig, &peig); 60123aa889a005 Dan Williams 2022-06-06 828 ways_to_cxl(parent_iw, &peiw); 60123aa889a005 Dan Williams 2022-06-06 829 60123aa889a005 Dan Williams 2022-06-06 830 iw = cxl_rr->nr_targets; 60123aa889a005 Dan Williams 2022-06-06 831 ways_to_cxl(iw, &eiw); 60123aa889a005 Dan Williams 2022-06-06 832 if (cxl_rr->nr_targets > 1) { 60123aa889a005 Dan Williams 2022-06-06 @833 u32 address_bit = max(peig + peiw, eiw + peig); 60123aa889a005 Dan Williams 2022-06-06 834 60123aa889a005 Dan Williams 2022-06-06 835 eig = address_bit - eiw + 1; 60123aa889a005 Dan Williams 2022-06-06 836 } else { 60123aa889a005 Dan Williams 2022-06-06 837 eiw = peiw; 60123aa889a005 Dan Williams 2022-06-06 838 eig = peig; 60123aa889a005 Dan Williams 2022-06-06 839 } 60123aa889a005 Dan Williams 2022-06-06 840 60123aa889a005 Dan Williams 2022-06-06 841 rc = cxl_to_granularity(eig, &ig); 60123aa889a005 Dan Williams 2022-06-06 842 if (rc) { 60123aa889a005 Dan Williams 2022-06-06 843 dev_dbg(&cxlr->dev, "%s:%s: invalid interleave: %d\n", 60123aa889a005 Dan Williams 2022-06-06 844 dev_name(port->uport), dev_name(&port->dev), 60123aa889a005 Dan Williams 2022-06-06 845 256 << eig); 60123aa889a005 Dan Williams 2022-06-06 846 return rc; 60123aa889a005 Dan Williams 2022-06-06 847 } 60123aa889a005 Dan Williams 2022-06-06 848 60123aa889a005 Dan Williams 2022-06-06 849 cxld->interleave_ways = iw; 60123aa889a005 Dan Williams 2022-06-06 850 cxld->interleave_granularity = ig; 60123aa889a005 Dan Williams 2022-06-06 851 dev_dbg(&cxlr->dev, "%s:%s iw: %d ig: %d\n", dev_name(port->uport), 60123aa889a005 Dan Williams 2022-06-06 852 dev_name(&port->dev), iw, ig); 60123aa889a005 Dan Williams 2022-06-06 853 add_target: 60123aa889a005 Dan Williams 2022-06-06 854 if (cxl_rr->nr_targets_set == cxl_rr->nr_targets) { 60123aa889a005 Dan Williams 2022-06-06 855 dev_dbg(&cxlr->dev, 60123aa889a005 Dan Williams 2022-06-06 856 "%s:%s: targets full trying to add %s:%s at %d\n", 60123aa889a005 Dan Williams 2022-06-06 857 dev_name(port->uport), dev_name(&port->dev), 60123aa889a005 Dan Williams 2022-06-06 858 dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos); 60123aa889a005 Dan Williams 2022-06-06 859 return -ENXIO; 60123aa889a005 Dan Williams 2022-06-06 860 } 60123aa889a005 Dan Williams 2022-06-06 861 cxlsd->target[cxl_rr->nr_targets_set] = ep->dport; 60123aa889a005 Dan Williams 2022-06-06 862 inc = 1; 60123aa889a005 Dan Williams 2022-06-06 863 out_target_set: 60123aa889a005 Dan Williams 2022-06-06 864 cxl_rr->nr_targets_set += inc; 60123aa889a005 Dan Williams 2022-06-06 865 dev_dbg(&cxlr->dev, "%s:%s target[%d] = %s for %s:%s @ %d\n", 60123aa889a005 Dan Williams 2022-06-06 866 dev_name(port->uport), dev_name(&port->dev), 60123aa889a005 Dan Williams 2022-06-06 867 cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dport), 60123aa889a005 Dan Williams 2022-06-06 868 dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos); 60123aa889a005 Dan Williams 2022-06-06 869 60123aa889a005 Dan Williams 2022-06-06 870 return 0; 60123aa889a005 Dan Williams 2022-06-06 871 } 60123aa889a005 Dan Williams 2022-06-06 872 -- 0-DAY CI Kernel Test Service https://01.org/lkp _______________________________________________ kbuild mailing list -- kbuild@lists.01.org To unsubscribe send an email to kbuild-le...@lists.01.org
