** Description changed:

  [Impact]
  Applications, particularly those in the HPC domain (e.g. openmpi), can be 
optimized for the processor and cache topology. However, the ARM CPU topology 
isn't correctly exposed to userspace.
  
  [Fix]
  The ACPI 6.2 specification introduced a Processor Properties Topology Table 
(PPTT). The linux kernel needs support for parsing this table, and exposing the 
parsed topology to userspace.
+ 
  [Test Case]
- TBD
+ A HiSilicon D06 without the fix:
+ 
+ ubuntu@d06-1:~$ lscpu
+ Architecture:        aarch64
+ Byte Order:          Little Endian
+ CPU(s):              96
+ On-line CPU(s) list: 0-95
+ Thread(s) per core:  1
+ Core(s) per socket:  4
+ Socket(s):           24
+ NUMA node(s):        4
+ Vendor ID:           0x48
+ Model:               0
+ Stepping:            0x0
+ BogoMIPS:            200.00
+ NUMA node0 CPU(s):   0-23
+ NUMA node1 CPU(s):   24-47
+ NUMA node2 CPU(s):   48-71
+ NUMA node3 CPU(s):   72-95
+ Flags:               fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid 
asimdrdm dcpop
+ 
+ With the fix:
+ ubuntu@d06-1:~$ lscpu
+ Architecture:        aarch64
+ Byte Order:          Little Endian
+ CPU(s):              96
+ On-line CPU(s) list: 0-95
+ Thread(s) per core:  1
+ Core(s) per socket:  48
+ Socket(s):           2
+ NUMA node(s):        4
+ Vendor ID:           0x48
+ Model:               0
+ Stepping:            0x0
+ BogoMIPS:            200.00
+ L1d cache:           64K
+ L1i cache:           64K
+ L2 cache:            512K
+ L3 cache:            32768K
+ NUMA node0 CPU(s):   0-23
+ NUMA node1 CPU(s):   24-47
+ NUMA node2 CPU(s):   48-71
+ NUMA node3 CPU(s):   72-95
+ Flags:               fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid 
asimdrdm dcpop
+ 
  
  [Regression Risk]
  TBD

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https://bugs.launchpad.net/bugs/1770231

Title:
  Expose arm64 CPU topology to userspace

Status in linux package in Ubuntu:
  In Progress
Status in linux source package in Bionic:
  New

Bug description:
  [Impact]
  Applications, particularly those in the HPC domain (e.g. openmpi), can be 
optimized for the processor and cache topology. However, the ARM CPU topology 
isn't correctly exposed to userspace.

  [Fix]
  The ACPI 6.2 specification introduced a Processor Properties Topology Table 
(PPTT). The linux kernel needs support for parsing this table, and exposing the 
parsed topology to userspace.

  [Test Case]
  A HiSilicon D06 without the fix:

  ubuntu@d06-1:~$ lscpu
  Architecture:        aarch64
  Byte Order:          Little Endian
  CPU(s):              96
  On-line CPU(s) list: 0-95
  Thread(s) per core:  1
  Core(s) per socket:  4
  Socket(s):           24
  NUMA node(s):        4
  Vendor ID:           0x48
  Model:               0
  Stepping:            0x0
  BogoMIPS:            200.00
  NUMA node0 CPU(s):   0-23
  NUMA node1 CPU(s):   24-47
  NUMA node2 CPU(s):   48-71
  NUMA node3 CPU(s):   72-95
  Flags:               fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid 
asimdrdm dcpop

  With the fix:
  ubuntu@d06-1:~$ lscpu
  Architecture:        aarch64
  Byte Order:          Little Endian
  CPU(s):              96
  On-line CPU(s) list: 0-95
  Thread(s) per core:  1
  Core(s) per socket:  48
  Socket(s):           2
  NUMA node(s):        4
  Vendor ID:           0x48
  Model:               0
  Stepping:            0x0
  BogoMIPS:            200.00
  L1d cache:           64K
  L1i cache:           64K
  L2 cache:            512K
  L3 cache:            32768K
  NUMA node0 CPU(s):   0-23
  NUMA node1 CPU(s):   24-47
  NUMA node2 CPU(s):   48-71
  NUMA node3 CPU(s):   72-95
  Flags:               fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid 
asimdrdm dcpop

  
  [Regression Risk]
  TBD

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