Hi everyone.
I'm currently in the process of doing a "JAVA" Machine core that can be put
in a FPGA. so JOS is rather interesting. Right now we are at about 30,000
gates. So far its clean-room.
The web-sites a bit non-functional, so could someone give me a nice overview
of current status.
On the memory model, a flat memory model is prefered in a embedded space,
where I'm looking at.
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Glenn West - Senior Member, Research Staff
Kent Ridge Digital Labs (KRDL)
Voice: (65) 874-8210 Fax: (65) 776-8109
21 Heng Mui Keng Terrace
Singapore 119613 Singapore
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Kernel maillist - [EMAIL PROTECTED]
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