The mechanism to disable the L1/L2 memory caches of the CPU will depend on the processor architecture itself. This can be possibly be done at kernel boot-time or more preferably, in your case, through a kernel module.
For Intel x86, the kernel module would look something like following: (The key is setting bit 30 of the control register cr0) mov eax,cr0 or eax, 40000000H ;set bit 30 without clearing the others mov cr0,eax Reference: http://stackoverflow.com/questions/1108485/disable-l2-l1-caches http://dirac.org/linux/writing/lkmpg/2.6/lkmpg-2.6.0.html ~ Gaurav On Tue, Feb 26, 2013 at 12:31 PM, sandeep kumar <coolsandyfor...@gmail.com>wrote: > Hi All > In performance benchmark tools, When we profile read/write timings mostly, > those read/writes are done to cache only. > > I want to measure my DDR(RAM chip) performance. > So i want to make sure, every read/write should happen to DDR RAM chip > only. > > How can i achieve this...Any ideas/suggestions...? > > -- > With regards, > Sandeep Kumar Anantapalli, > > _______________________________________________ > Kernelnewbies mailing list > Kernelnewbies@kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > > -- Gaurav Jain Associate Software Engineer VxVM Escalations Team, SAMG Symantec Software India Pvt. Ltd.
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