Thanks, I'll check it out. On Sat, 11 Jan, 2020, 4:33 AM Onur Atilla, <[email protected]> wrote:
> On 10.01.20 15:58, Muni Sekhar wrote: > > On Fri, Jan 10, 2020 at 4:46 PM Primoz Beltram <[email protected]> > wrote: > >> > >> Hi, > >> Have read also other replays to this topic. > >> I have seen-debug such deadlock problems with FPGA based PCIe endpoint > >> devices (Xilinx chips) and usually (if not signal integrity problems), > >> the problem was in wrong AXI master/slave bus handling in FPGA design. > >> I guess you have FPGA Xilinx PCIe endpoint IP core attached as AXI > >> master to FPGA internal AXI bus (access to AXI slaves inside FPGA > design). > >> If FPGA code in your design does not handle correctly AXI master > >> read/write requests, e.g. FPGA AXI slave does not generate bus ACK in > >> correct way, the PCIe bus will stay locked (no PCIe completion sent > >> back), resulting in complete system lock. Some PCIe root chips have > >> diagnostic LEDs to help decode PCIe problems. > >> From your notice about doing two 32bit reads on 64bit CPU, I would > >> guess the problem is in handling AXI transfer size signals in FPGA slave > >> code. > >> I would suggest you to check the code in FPGA design. You can use FPGA > >> test bench simulation to check the behaviour of PCIe endpoint originated > >> AXI read/write requests. > >> Xilinx provides test bench simulation code for their PCIe IP's. > >> They provide also PCIe root port model, so you can simulate AXI > >> read/writes accesses as they would come from CPU I/O memory requests via > >> PCIe TLPs. > > Thank you so much for sharing valuable information, will work on this. > > > >> WBR Primoz > > Hi, > > you may also want to have a look at the AXI Timeout Block (ATB) to > prevent system/core locks due to a missing ACK of a slave. If given by > the HW, ATB generates an alternative response in case the slave fails to > respond within a given time. It may also trigger an interrupt to help > handle/debug the error. > > Regards, > Onur > >
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