Documentation about memory-barriers.txt gives a very good explanation.
http://lxr.linux.no/linux+v2.6.30/Documentation/memory-barriers.txt
thanks
BRs.
Lin
2009/7/19 Peter Teoh <htmldevelo...@gmail.com>:
> thank you for the reference....and sharing...
>
> On Sun, Jul 19, 2009 at 9:52 PM, Pei Lin<telent...@gmail.com> wrote:
>> on X86 architecture u can refer to "
>> Intel® 64 and IA-32 Architectures Software Developer's Manual
>> Volume 3A: System Programming Guide"
>> chapter 11 memory cache control 11.5.5 Cache Management instructions.
>> CLFLUSH
>>
>> BRs,
>>
>> Lin
>>
>
> perhaps i can share with you:
>
> From arch/x86/mm/pageattr.c I found this:
>
> 119 /*
> 120 * Flushing functions
> 121 */
> 122
> 123 /**
> 124 * clflush_cache_range - flush a cache range with clflush
> 125 * @addr: virtual start address
> 126 * @size: number of bytes to flush
> 127 *
> 128 * clflush is an unordered instruction which needs fencing with mfence
> 129 * to avoid ordering issues.
> 130 */
> 131 void clflush_cache_range(void *vaddr, unsigned int size)
> 132 {
> 133 void *vend = vaddr + size - 1;
> 134
> 135 mb();
> 136
> 137 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
> 138 clflush(vaddr);
> 139 /*
> 140 * Flush any possible final partial cacheline:
> 141 */
> 142 clflush(vend);
>
> So mfence is needed before clflush??? first time I read this part of
> the code too!!!!
>
>
> --
> Regards,
> Peter Teoh
>
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