Hi Cirilo,
attached the pcb board with the module with oval holes...
is it what you need?
thank you
Maurice
On 04/07/2015 11.20, Cirilo Bernardo wrote:
Hi Maurice,
The IDF export is wrong. If you can file a bug report with detailed
instructions on how to reproduce the problem with the incorrect slot width
that would be helpful. At the moment I can only reproduce the incorrect
orientation of the slot.
- Cirilo
On Sat, Jul 4, 2015 at 4:56 PM, easyw <ea...@katamail.com> wrote:
Hi Cirilo,
thanks for your feedback!
to install the new freecad in debian I think it could be done with:
sudo add-apt-repository -y ppa:freecad-maintainers/freecad-stable
sudo apt-get update
sudo apt-get install freecad
(at least it worked for me in ubuntu where I had freecad 0.14)
I have tried to export to IDF a board with a module with oval pads with
oval holes
I attached the board and IDF file
I seems that x and y are switched in the holes and the third hole also has
one incorrect diameter...
could you please check if the problem is in the interpreting in freecad of
the file (I do not have solid works to check it) or if is a small bug in
the exporter?
thank you very much again for you advices :)
Maurice
On 04/07/2015 02.05, Cirilo Bernardo wrote:
Thanks Maurice,
Maybe you should also post to the user list. I'm sure everyone who needs
solid models will find it useful and you would get more testing done as
well; I'm finding it very difficult to find time to do even simple testing
at the moment and I haven't built FreeCAD for a few years now so I only
have what's available on Debian (0.14).
This looks very good and will be very useful and is much less hassle
than
the process which many people use to convert their VRML models to a solid
model. It will still be many months yet before KiCad has a native solid
model export which I'm guessing will be IGES at this point, and who knows
how much longer it will be before someone finds time to add STEP. The
combination of IDF + STEP is good since the solid model of the PCB will
actually have circular drill holes which can be used by MCADs as a
reference point; models derived from VRML rendering of the board always
give polygonal holes which are frustrating to work with in MCAD.
- Cirilo
On Fri, Jul 3, 2015 at 7:08 PM, easyw <ea...@katamail.com> wrote:
Hi Cirilo,
I've uploaded the recent version of the script with the demo board at
sourceforge
https://sourceforge.net/projects/kicadstepup/?source=navbar
(I know I should have done in launchpad but I'm not familiar with bzr
etc... I promise I will learn it)
In the updated script I've put some check for the presence of files and
models, so to give messages to the user...
there is a readme file
http://sourceforge.net/projects/kicadstepup/files/README.txt/download
and the demo folder with all files
http://sourceforge.net/projects/kicadstepup/files/kicad_StepUp_v0.42.zip/download
the script is a python script for freecad (kicad_StepUp.FCMacro)
just move to the demo dir and launch
freecad demo.emn kicad_StepUp.FCMacro
(the demo.emn is the IDF file exported through your IDF routines)
here there is also a link of the script in action...
http://youtu.be/Ukd47VXYzQU
the trick to obtain the hierarchical STEP file from freecad 0.15 is to
use
export 'STEP with colors' from File menu (NOT from Part menu)
Please have a try at the demo and eventually with some of your kicad
projects and let me know your feedback ...
thank you
Maurice
On 03/07/2015 00.39, Cirilo Bernardo wrote:
Hi Maurice,
This is good in SolidWorks as well; I have a few questions:
Where is this FreeCAD script to process the files and create the
assembly?
What is the secret to making OCC/FreeCAD create a hierarchical STEP file
rather than a flat file?
- Ciirlo
On Thu, Jul 2, 2015 at 7:28 PM, easyw <ea...@katamail.com
<mailto:ea...@katamail.com>> wrote:
@Tom
Hi Tom, following your advices (design in STEP B-Rep)
I came with this approach:
- prepare or just download STEP models for 3D parts
- convert STEP to VRML to build the pcb in kicad (using FreeCAD)
- just place pcb parts in kicad as always
- export IDF pcb plain board
- assembly automatically the board in MCAD reading 3D modules and
positions from kicad pcb file with the kicad_StepUp script
- export the STEP assembly from MCAD (using FreeCAD)
I asked a friend of mine to import the result in SolidWorks and it
seems to be fine...
Could you please check if the result (demo.step) it is fine in
hierarchical STEP assembly?
Thank you very much
Maurice
On 01/07/2015 23.49, easyw wrote:
Hi,
kicad StepUp is a new approach to export kicad board and
modules
in STEP
AP214 (with colors)
exporting needs these requirements:
1) install FreeCAD 0.15
1b) in windows copy the Idf.py patched file in
FreeCAD/Mod/Idf
folder (in Linux IDF import seems fine)
2) start your 3D module model design directly in STEP using
FreeCAD or
just getting the model from a STEP library
(units mm required)
3) put your STEP model in the same directory in which are
normally the
wrl models
4) convert your 3D STEP model in vrml through FreeCAD
(scaling it to 0.3937, a kicad_StepUp_vrml_export macro is
provided
just launch e.g. freecad sot23.step
kicad_StepUp_vrml_export.FCMacro)
4) in pcbnew just populate your board as usual, using only vrml
models
with the corresponding model in STEP
5) export the plain board through IDF menu (no IDF models are
needed,
just wrl standard ones)
6) move to the 'demo' dir and execute the python kicad_StepUp
FCMacro
launching:
freecad demo.emn kicad_StepUp.FCMacro
(in windows you may need to specify freecad.exe bin
path)
and wait until your 3D board will be automatically
populated following kicad_pcb source board
(note only kicad_pcb version 4 is supported)
7) the script can be configured to follow the KISYS3DMOD path
Please consider that the project is at alpha state and not
everything
has been completed
(e.g. at the moment Bottom items do not respect orientation,
and Top orientation is referred only to pcb module, assuming
wrl
module ha the same orientation
the script will stop in case of missing modules without any
message)
I would need someone to check if the models used and the
resulting
demo.step obtained from the elaboration
is fine to be used in MCAD e.g. SolidWorks that I do not
have...
I checked the result with a trial of Catia and Rhino and it
seems fine...
If the result is fine to be used in MCAD the refined script
could
be
used to convert the pcb artworks for 3D MCAD modelling, and
could
be
easily ready to go for the stable release....
The only requirements, different from the actual way of using
kicad is
to substitute Wings3D with FreeCAD and, obviously, populate
the 3D
models with STEP lib...
(anyway Wings3D can be used besides FreeCAD if the 3D STEP
exporting it
is not needed)
attached a kicad demo project, with self containing STEP and
wrl
modules
to be used just out of the box,
some screen-shots of the result
here there is also a link of the script in action...
http://youtu.be/Ukd47VXYzQU
thank you for any suggestion and feedback,
Maurice
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(kicad_pcb (version 4) (host pcbnew "(2015-07-01 BZR 5852)-product")
(general
(links 0)
(no_connects 0)
(area 109.029499 129.349499 144.970501 155.130501)
(thickness 1.6002)
(drawings 4)
(tracks 0)
(zones 0)
(modules 1)
(nets 1)
)
(page A4)
(layers
(0 Front signal)
(31 Back signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
)
(setup
(last_trace_width 0.2032)
(trace_clearance 0.254)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2032)
(segment_width 0.381)
(edge_width 0.381)
(via_size 0.889)
(via_drill 0.635)
(via_min_size 0.889)
(via_min_drill 0.508)
(uvia_size 0.508)
(uvia_drill 0.127)
(uvias_allowed no)
(uvia_min_size 0.508)
(uvia_min_drill 0.127)
(pcb_text_width 0.3048)
(pcb_text_size 1.524 2.032)
(mod_edge_width 0.381)
(mod_text_size 1.524 1.524)
(mod_text_width 0.3048)
(pad_size 1.524 1.524)
(pad_drill 0.8128)
(pad_to_mask_clearance 0.254)
(aux_axis_origin 0 0)
(visible_elements 7FFFFFFF)
(pcbplotparams
(layerselection 0x00030_80000001)
(usegerberextensions true)
(excludeedgelayer true)
(linewidth 0.150000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 0)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net_class Default "This is the default net class."
(clearance 0.254)
(trace_width 0.2032)
(via_dia 0.889)
(via_drill 0.635)
(uvia_dia 0.508)
(uvia_drill 0.127)
)
(net_class pwr ""
(clearance 0.254)
(trace_width 1.00076)
(via_dia 1.80086)
(via_drill 0.89916)
(uvia_dia 0.508)
(uvia_drill 0.127)
)
(net_class pwr1 ""
(clearance 0.254)
(trace_width 0.50038)
(via_dia 0.889)
(via_drill 0.635)
(uvia_dia 0.508)
(uvia_drill 0.127)
)
(module a_CONNECTORS:JACK_ALIM_RV-round-drlplt-backCu4 (layer Front) (tedit
5538FC80) (tstamp 5596A64E)
(at 121.92 140.97)
(descr "connector jack")
(tags "CONN JACK")
(fp_text reference J*** (at 1.905 -6.35) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.254)))
)
(fp_text value DC_JACK_R_V_drill_plated (at 2.54 8.89) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.254)))
)
(fp_line (start -1.651 0) (end -1.651 -1.27) (layer F.SilkS) (width
0.29972))
(fp_line (start -1.651 -1.27) (end 0.762 -2.286) (layer F.SilkS) (width
0.29972))
(fp_line (start 0.762 -2.286) (end 3.175 -1.27) (layer F.SilkS) (width
0.29972))
(fp_line (start 3.175 -1.27) (end 3.175 0) (layer F.SilkS) (width 0.29972))
(fp_line (start 3.175 4.445) (end 3.175 0) (layer F.SilkS) (width 0.29972))
(fp_line (start -1.651 4.445) (end -1.651 0) (layer F.SilkS) (width
0.29972))
(fp_line (start 7.5565 4.572) (end 7.5565 -4.572) (layer F.SilkS) (width
0.29972))
(fp_line (start -3.4925 4.572) (end 7.5565 4.572) (layer F.SilkS) (width
0.29972))
(fp_line (start -3.4925 -4.572) (end -3.4925 4.572) (layer F.SilkS) (width
0.29972))
(fp_line (start -3.4925 -4.572) (end 7.5565 -4.572) (layer F.SilkS) (width
0.29972))
(pad 1 thru_hole oval (at 0.762 4.318) (size 5 3.5) (drill oval 3.1 2.5)
(layers *.Cu *.Mask F.SilkS))
(pad 2 thru_hole oval (at 6.35 1.524) (size 2.5 3.8) (drill oval 1.5 2.8)
(layers *.Cu *.Mask F.SilkS))
(pad 3 thru_hole oval (at 2.921 -1.397) (size 2.5 3.8) (drill oval 1.5 2.8)
(layers *.Cu F.SilkS F.Mask)
(solder_mask_margin -0.5))
(pad 3 thru_hole oval (at 2.921 -1.397) (size 2.5 3.8) (drill oval 1.5 2.8)
(layers *.Cu B.Mask))
(model discrete/dc9-jack21-vert-r2b.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(gr_line (start 109.22 154.94) (end 109.22 129.54) (angle 90) (layer
Edge.Cuts) (width 0.381))
(gr_line (start 144.78 154.94) (end 109.22 154.94) (angle 90) (layer
Edge.Cuts) (width 0.381))
(gr_line (start 144.78 129.54) (end 144.78 154.94) (angle 90) (layer
Edge.Cuts) (width 0.381))
(gr_line (start 109.22 129.54) (end 144.78 129.54) (angle 90) (layer
Edge.Cuts) (width 0.381))
)
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