Bens code looks good, and seems to do a lot that I am trying to achieve
with my python scripts. I am not sure what state its in with regard to
integrating it with the latest KiCad. But I would be keen to see it happen.
With regard to the patch I propose, the referenced code implements a
scheme to "Lock" a net to a Track/Via which is a good enhancement.
My patch does a slightly different thing, it remembers what net every
track/via was on, and at the end of reassigning nets will restore the
previously assigned net, but only if it failed to acquire a net during
the net reassignment scan.
So the "Lock Net" enhancement is a "Hard Net", reassignment will never
change it. Even if this would result in a DRC Error.
My proposal is a "Softer Net", in that all nets which cant be
automatically reassigned will survive reassignment, so if it needs to be
reassigned it will be, but otherwise it wont change.
I think they are both worth while enhancements.
If my patch is "up to snuff", I can look at bringing the "Locked Net"
patch across to the latest code base. The rest of the RF enhancements
worked on by Ben all require it as a pre-requisite, but as a general
enhancement its very useful.
Steven
On 13/12/15 07:05, easyw wrote:
Hi Steven,
Ben has developed some code for RF design...
https://lists.launchpad.net/kicad-developers/msg19528.html
https://lists.launchpad.net/kicad-developers/pngMPwkPIbzFA.png
may be you could work together for a merging patch :)
PS please keep me informed :)
On 12/12/2015 02.41, Strontium wrote:
I am working on a couple of RF designs, proper layout requires the use
of "Via Curtains/Via Filling", Further they are HDI boards and I am
using both through-hole and micro vias.
I am aware of the "Pro Tip" which suggests simulating a via with a
component with a single pad. The "Pro-Tip" doesn't work for me, because
a pad simulates a through hole via only, and I also need to fill with
micro-vias.
I am attempting to write python scripts to automate the Via
Curtain/Filling, which is otherwise tedious and difficult to edit.
However, there is existing behaviour of Kicad which will cause it to
delete the net associated with a Track/Via unless that Track/Via is
connected to a pad, after a DRC.
This behaviour stems from the function :
void PCB_BASE_FRAME::RecalculateAllTracksNetcode()
in pcbnew/connect.cpp
Basically it traces all tracks/vias from the pads and reassigns their
nets based on the pads they are connected to. To do that, it first
removes the already associated nets, and uses the "unassigned net" as a
flag to tell the function what needs to be traced.
This is fine, and works well. But in the circumstance where the
Via/Track is not actually connected to a pad it has the side-effect,
once complete, of leaving those vias/tracks in the "unconnected" state.
The reality is, these vias/tracks are not "unconnected" the designer has
actually connected them to the fill planes, or otherwise assigned them a
net for a reason, which this function does not account for, and doing so
would be non-trivial and prone to error.
(For example, a Board with a GND/VCC/GND/VCC four layer fill could use a
through via to connect the GND planes, OR the VCC planes and there is no
way to automatically determine which.)
Instead, I propose the following patch, or something like it, which
simply "backs up" the nets of the tracks/vias and after the Nets are
recalculated, for those which were not changed, restores their net to
the one it was on entry.
This means if the designer places a GND Via not connected to a pad, it
will always be a GND Via and will never "lose" its net on DRC. It will
then properly connect the Fill Planes or whatever other purpose the
designer had in mind, and wont change.
This change should not break or modify any current behaviour, EXCEPT to
retain the nets of tracks/vias which Kicad is otherwise incapable of
determining automatically.
Strontium (Steven J)
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