Hi Jean-Pierre,
I have done several designs with KiCad and stitch vias. The simplest way for me is to create a module with a single through hole pad.
I've even written a python script to automate the placement of these stitch vias (see the mailing list archive). That was never a big problem and works well with the stable KiCad version, no issues with zone filling or net calculations.
I'm guessing that Altium PCB using a special primitive for stitch vias as well.
See http://techdocs.altium.com/display/ADOH/Via+Stitching
Only blind vias or burried vias are not possible when using a single pad module; Altium uses the start and end layer as attribute for these purposes.
--
So maybe having free pads with similar attributes - like Altium is using - is here an alternative solution. Also for mounting holes as well (currently you need to create a module for them).
Thanks,
Torsten
When this entity is defined, netnames will be no more a problem.
So: first, define what is this entity (The best choice is not trivial for me, and deserves to think
about it), how vias are linked to (or owned by) this entity, how they are taken in account by DRC
and zone filling algorithms, and only after see if net names issues still exist.
So: first, define what is this entity (The best choice is not trivial for me, and deserves to think
about it), how vias are linked to (or owned by) this entity, how they are taken in account by DRC
and zone filling algorithms, and only after see if net names issues still exist.
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