Chuck Esterbrook wrote:
I think banging into edge cases is inevitable when trying to use a
general purpose language as a so-called domain specific language
(DSL). Furthermore, the amount of hassles you run into is somewhat
arbitrary with respect to the specifics of the general purpose
language, the specific domain and the pickiness of the users.
Maybe. But I'm not convinced it has to be.
In this instance, the issue is why use Python+MyHDL rather than
SystemVerilog. The answer is that while SystemVerilog is "better" than
Python at the core hardware abstractions, Python kicks SystemVerilog's
butt 8 ways from Sunday the moment you step outside basic hardware
abstractions because it's got a *huge* library.
Basically, the ease of testing and debugging something using Python and
its libraries completely swamps any ease of coding the original hardware
in SystemVerilog.
A different approach is to create a new language, possibly translating
it over to something high level like Python, Java, etc. for the
benefits thereof (gc, libs, etc.).
I'm not convinced that's a win. You're still stuck with the underlying
semantics unless you're effectively creating your own VM loop. I
presume that's why you created Cobra's runtime rather than translating
to Python/C#/etc.
-- May 2008 Python Magazine has an article on writing an
interpreter/compiler with Pyparsing
-- The OMeta project strives to make building new languages easier.
-- http://www.cs.ucla.edu/~awarth/ometa/
-- EasyExtend lets you extend Python.
-- http://www.fiber-space.de/EasyExtend/doc/EE.html
I will have a look at these.
-a
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