Avi Kivity wrote:
> Earlier we check if the accessed bit is off, and if so, we
> don't set the
> shadow pte. This won't happen in practice because the guest's page
> fault handler will set the accessed bit when it modifies a pte
> to avoid
> an RMW cycle by the hardware page table walker.
>
Thanks! That is good enough.
BTW, in kvm_mmu_pte_write, I feel a little bit stranger for following
code:
> level = page->role.level;
> npte = 1;
> if (page->role.glevels == PT32_ROOT_LEVEL) {
> page_offset <<= 1; /* 32->64 */
> /*
> * A 32-bit pde maps 4MB while the shadow pdes
> map
> * only 2MB. So we need to double the offset
> again
> * and zap two pdes instead of one.
> */ if (level == PT32_ROOT_LEVEL) {
> page_offset &= ~7; /* kill rounding
> error */ page_offset <<= 1;
> npte = 2;
1st of all, do we have 2MB pde in shadow PT? I think we don't provide
contiguous physical mfn for shadow PT.
If page->role.level == PT32_ROOT_LEVEL, sequencial call of
mmu_pte_write_new_pte will simply return w/o any real spte operation.
Does this ever happen w/ a real spte write?
I tried a 32 bits FC5 with no found of this combination till Linux boot.
> }
> quadrant = page_offset >> PAGE_SHIFT;
> page_offset &= ~PAGE_MASK;
> if (quadrant != page->role.quadrant)
> continue;
> }
> spte = &page->spt[page_offset / sizeof(*spte)];
> while (npte--) {
> mmu_pte_write_zap_pte(vcpu, page, spte);
> mmu_pte_write_new_pte(vcpu, page,
> spte, new, bytes);
If above comments is correct, we need to provide an increased (gfn) gpte
so that the next 2MB spte can have right gfn from gpte. Am I missing
something?
> ++spte;
> }
Thx,eddie
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