Intel manual (and KVM definition) say it's TPR is 4 bits wide. Also fix
CR8_RESEVED_BITS typo.
Signed-off-by: Rusty Russell <[EMAIL PROTECTED]>
diff -r 6ef0b4c0d6f7 drivers/kvm/kvm_main.c
--- a/drivers/kvm/kvm_main.c Tue Jul 17 18:07:48 2007 +1000
+++ b/drivers/kvm/kvm_main.c Tue Jul 17 18:20:22 2007 +1000
@@ -92,7 +92,7 @@ static struct dentry *debugfs_dir;
| X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
| X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
-#define CR8_RESEVED_BITS (~0x0fULL)
+#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
#define EFER_RESERVED_BITS 0xfffffffffffff2fe
#ifdef CONFIG_X86_64
@@ -633,7 +633,7 @@ EXPORT_SYMBOL_GPL(set_cr3);
void set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
{
- if ( cr8 & CR8_RESEVED_BITS) {
+ if (cr8 & CR8_RESERVED_BITS) {
printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
inject_gp(vcpu);
return;
diff -r 6ef0b4c0d6f7 include/asm-i386/processor-flags.h
--- a/include/asm-i386/processor-flags.h Tue Jul 17 18:07:48 2007 +1000
+++ b/include/asm-i386/processor-flags.h Tue Jul 17 18:12:54 2007 +1000
@@ -63,7 +63,7 @@
/*
* x86-64 Task Priority Register, CR8
*/
-#define X86_CR8_TPR 0x00000007 /* task priority register */
+#define X86_CR8_TPR 0x0000000F /* task priority register */
/*
* AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
-------------------------------------------------------------------------
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