Regular pci irq is level triggered, thus must be acked by port io/
mmio. For PV devices it's a bad idea since it will trigger a costly
VM exit.
This hack add ability to trigger pic/apic irqs.
Signed-off-by: Dor Laor <[EMAIL PROTECTED]>
---
qemu/hw/apic.c | 10 ++++++++++
qemu/hw/i8259.c | 19 +++++++++++++++++++
2 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/qemu/hw/apic.c b/qemu/hw/apic.c
index dc92f8a..76fc3b9 100644
--- a/qemu/hw/apic.c
+++ b/qemu/hw/apic.c
@@ -948,6 +948,16 @@ void ioapic_set_irq(void *opaque, int vector, int
level)
}
}
+void ioapic_mark_as_edge_triggered(void *opaque, int vector)
+{
+ IOAPICState *s = opaque;
+
+ if (vector >= 0 && vector < IOAPIC_NUM_PINS)
+ {
+ s->ioredtbl[vector] &= ~(1 << 15);
+ }
+}
+
static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
{
IOAPICState *s = opaque;
diff --git a/qemu/hw/i8259.c b/qemu/hw/i8259.c
index a2a8187..ace67c6 100644
--- a/qemu/hw/i8259.c
+++ b/qemu/hw/i8259.c
@@ -93,6 +93,25 @@ static inline void pic_set_irq1(PicState *s, int irq,
int level)
}
}
+void paravirt_set_irq(int irq)
+{
+ PicState *s = &isa_pic->pics[irq >> 3];
+ int mask = 1 << (7 & irq);
+
+ /* Force it to be edge triggered */
+ s->elcr &= ~mask;
+ s->irr |= mask;
+
+ if (isa_pic->alt_irq_func && isa_pic->alt_irq_opaque)
+ {
+ /* Force it to be edge triggered */
+ ioapic_mark_as_edge_triggered(isa_pic->alt_irq_opaque,
irq);
+ isa_pic->alt_irq_func(isa_pic->alt_irq_opaque, irq, 1);
+ }
+
+ pic_update_irq(isa_pic);
+}
+
/* return the highest priority found in mask (highest = smallest
number). Return 8 if no irq */
static inline int get_priority(PicState *s, int mask)
-----
In simplicity there is elegance.
Dor Laor ;)
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