Hi,
sorry for the delay, but I've been on vacation. :-)
On Sun, 30 Sep 2007, Anthony Liguori wrote:
> Avi Kivity wrote:
> > Anthony Liguori wrote:
> >> As Avi pointed out, VT requires that SS.RPL == CS.RPL. We're seeing
> >> gfxboot fail under KVM because ss = 0x5761 while cs = 0x4004 during
> >> the transition from real mode to protected mode. The attached patch
> >> passes the value of ss through ebx since KVM has to sanitize the value
> >> of ss to make VT happy.
Uh, that's weird! Thanks for pointing this out.
[patch]
> > This is subtly wrong, I think. First, note that 'mov eax,ss' only
> > affects ax, not the high 16 bits. The note that the original code
> > happily shifts eax which is half ss, half garbage left by 4 bits and
> > uses that to generate a 32-bit result.
> >
> > The reason it worked before was that bits 16-29 of eax are already clear
> > by virtue of having come from cr0. But now you're using ebx which
> > hasn't had that magic clearing.
> >
>
> You're right. Good catch!
Actually that is not true. 'mov eax,ss' does implicitly clear the upper
16 bits (both processor docs and hardware agree here).
> > In your comment to the kvm bug you say that the patch allows you to
> > boot, so perhaps bits 16-29 of ebx are already clear here, or my
> > analysis is mistaken.
> >
>
> Yeah, I just got lucky with ebx I guess :-) Attached is an updated patch that
> fixes this problem.
Anyway, ss is already saved, so no need for an extra register. Here is
my version (tested and works on my machine):
--- bincode.asm (revision 650)
+++ bincode.asm (working copy)
@@ -15546,7 +15546,11 @@
mov ax,pm_seg.prog_d16
mov ds,ax
- mov eax,ss
+ ; needed for KVM:
+ ; ss:rpl must equal cs:rpl in PM for VT. We can't rely on ss
+ ; maintaining its value after the transition.
+
+ movzx eax,word [rm_seg.ss]
and esp,0ffffh
shl eax,4
add esp,eax
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