Hollis Blanchard wrote: > On Thu, 2008-01-10 at 08:56 +0200, Avi Kivity wrote: > >> IIRC endianness is a per-page attribute on ppc, no? Otherwise you'd >> have a global attribute instead of per-access. >> > > The MMU in some PowerPC can have per-page endianness, but not all. On a > processor that supports this attribute, I expect that when an MMIO trap > occurs we'll need to inspect the guest MMU state in order to set the > is_bigendian flag correctly. > > The real issue I'm looking at right now is byte-reversed loads and > stores. For example, "lwzx" (Load Word and Zero Indexed) does a > big-endian 4-byte load, while "lwbrx" (Load Word Byte-Reverse Indexed) > does a little-endian 4-byte load. These instructions exist on all > PowerPC, and they can be issued at any time and do not depend on MMU > mappings. >
Okay, so it's at instruction granularity _and_ page granularity. I'll apply that patch (with a #ifdef CONFIG_PPC so other archs don't use it by mistake). -- error compiling committee.c: too many arguments to function ------------------------------------------------------------------------- Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace _______________________________________________ kvm-devel mailing list kvm-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/kvm-devel
