Alexander Graf <ag...@suse.de> writes: > On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote: >> Alexander Graf <ag...@suse.de> writes: >> >>> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote: >>>> Although it's optional IBM POWER cpus always had DAR value set on >>>> alignment interrupt. So don't try to compute these values. >>>> >>>> Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com> >>>> --- >>>> Changes from V3: >>>> * Use make_dsisr instead of checking feature flag to decide whether to use >>>> saved dsisr or not >>>> >> .... >> >>>> ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst) >>>> { >>>> +#ifdef CONFIG_PPC_BOOK3S_64 >>>> + return vcpu->arch.fault_dar; >>> How about PA6T and G5s? >>> >>> >> Paul mentioned that BOOK3S always had DAR value set on alignment >> interrupt. And the patch is to enable/collect correct DAR value when >> running with Little Endian PR guest. Now to limit the impact and to >> enable Little Endian PR guest, I ended up doing the conditional code >> only for book3s 64 for which we know for sure that we set DAR value. > > Yes, and I'm asking whether we know that this statement holds true for > PA6T and G5 chips which I wouldn't consider IBM POWER. Since the G5 is > at least developed by IBM, I'd assume its semantics here are similar to > POWER4, but for PA6T I wouldn't be so sure.
I will have to defer to Paul on that question. But that should not prevent this patch from going upstream right ? -aneesh -- To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html