These two registers are already saved in the block above. Aside from
being unnecessary, by the time we get down to the second save location
r8 no longer contains MMCR2, so we are clobbering the saved value with
PMC5.
MMCR2 primarily consists of counter freeze bits. So restoring the value
of PMC5 into MMCR2 will most likely have the effect of freezing
counters.
Fixes: 72cde5a88d37 ("KVM: PPC: Book3S HV: Save/restore host PMU registers that
are new in POWER8")
Cc: sta...@vger.kernel.org
Signed-off-by: Joel Stanley <j...@jms.id.au>
Acked-by: Michael Ellerman <m...@ellerman.id.au>
Acked-by: Paul Mackerras <pau...@samba.org>
Reviewed-by: Alexander Graf <ag...@suse.de>
---
V2:
- Add comments from mpe
arch/powerpc/kvm/book3s_hv_interrupts.S | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv_interrupts.S
b/arch/powerpc/kvm/book3s_hv_interrupts.S
index 8c86422..731be74 100644
--- a/arch/powerpc/kvm/book3s_hv_interrupts.S
+++ b/arch/powerpc/kvm/book3s_hv_interrupts.S
@@ -127,11 +127,6 @@ BEGIN_FTR_SECTION
stw r10, HSTATE_PMC + 24(r13)
stw r11, HSTATE_PMC + 28(r13)
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
-BEGIN_FTR_SECTION
- mfspr r9, SPRN_SIER
- std r8, HSTATE_MMCR + 40(r13)
- std r9, HSTATE_MMCR + 48(r13)
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
31:
/*
--
2.0.0
--
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