On 9/23/08, David Miller <[EMAIL PROTECTED]> wrote: > From: Hollis Blanchard <[EMAIL PROTECTED]> > > Date: Mon, 22 Sep 2008 16:27:40 -0500 > > > > On Mon, 2008-09-22 at 15:31 -0500, Javier Guerra wrote: > > > On Mon, Sep 22, 2008 at 3:18 PM, Hollis Blanchard <[EMAIL PROTECTED]> > wrote: > > > > It would be even more interesting to implement host support on the > Sparc > > > > processors with hardware virtualization support. > > > > > > Does Sparc processors also have 'virtualization support' as an extra > > > feature? i thought that 'non virtualizationability' was an > > > intel-specific limitation. (come on... creating a privileged mode and > > > not trapping violations? who else would design like that?) > > > > Trapping on privileged instructions is enough to get you virtualization > > functionality, but for good performance you really want additional > > hardware support to avoid those traps in the first place. > > > That's not really available on sparc.
Looking at other intercept possibilities in AMD SVM, I'm not sure what would increase performance anyway except IO support. Because there are no dedicated IO instructions (except maybe some ASI accesses), the guest can be given direct HW access just by mapping the pages to guest address space (and adding IOMMU TLBs). -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
