Avi Kivity wrote:
> [EMAIL PROTECTED] wrote:
>> LINT0 of the LAPIC can be used to route PIT events as NMI watchdog ticks
>> into the guest. This patch aligns the in-kernel irqchip emulation with
>> the user space irqchip with already supports this feature. The trick is
>> to route PIT interrupts to all LAPIC's LVT0 lines.
>>
>> Rebased and slightly polished patch originally posted by Sheng Yang.
>>
>> Signed-off-by: Jan Kiszka <[EMAIL PROTECTED]>
>> Signed-off-by: Sheng Yang <[EMAIL PROTECTED]>
>> ---
>> arch/x86/kvm/i8254.c | 15 +++++++++++++++
>> arch/x86/kvm/irq.h | 1 +
>> arch/x86/kvm/lapic.c | 34 +++++++++++++++++++++++++++++-----
>> 3 files changed, 45 insertions(+), 5 deletions(-)
>>
>> Index: b/arch/x86/kvm/i8254.c
>> ===================================================================
>> --- a/arch/x86/kvm/i8254.c
>> +++ b/arch/x86/kvm/i8254.c
>> @@ -594,10 +594,25 @@ void kvm_free_pit(struct kvm *kvm)
>>
>> static void __inject_pit_timer_intr(struct kvm *kvm)
>> {
>> + struct kvm_vcpu *vcpu;
>> + int i;
>> +
>> mutex_lock(&kvm->lock);
>> kvm_set_irq(kvm, 0, 1);
>> kvm_set_irq(kvm, 0, 0);
>> mutex_unlock(&kvm->lock);
>> +
>> + /*
>> + * Provides NMI watchdog support in IOAPIC mode.
>> + * The route is: PIT -> PIC -> LVT0 in NMI mode,
>> + * timer IRQs will continue to flow through the IOAPIC.
>> + */
>> + for (i = 0; i < KVM_MAX_VCPUS; ++i) {
>> + vcpu = kvm->vcpus[i];
>> + if (!vcpu)
>> + continue;
>> + kvm_apic_local_deliver(vcpu, APIC_LVT0);
>> + }
>> }
>>
>
> It would be better to gate this on a variable which is set only if this
> is actually necessary (e.g, does any vcpu have LVT0 set to NMI mode).
> Otherwise, we touch all vcpus up to 1000 times a second. As this is an
> optimization, it can be done later.Good idea, will cook an add-on patch. Jan
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