POWER8 introduces transactional memory which brings along a number of new
registers and MSR bits.
Implementing all of those is a pretty big headache, so for now let's at least
emulate enough to make Linux's context switching code happy.
Signed-off-by: Alexander Graf <ag...@suse.de>
---
arch/powerpc/kvm/book3s_emulate.c | 18 ++++++++++++++++++
arch/powerpc/kvm/book3s_pr.c | 3 ++-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/book3s_emulate.c
b/arch/powerpc/kvm/book3s_emulate.c
index d1ad257..870d9b8 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -450,6 +450,15 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu,
int sprn, ulong spr_val)
case SPRN_EBBRR:
vcpu->arch.ebbrr = spr_val;
break;
+ case SPRN_TFHAR:
+ vcpu->arch.tfhar = spr_val;
+ break;
+ case SPRN_TEXASR:
+ vcpu->arch.texasr = spr_val;
+ break;
+ case SPRN_TFIAR:
+ vcpu->arch.tfiar = spr_val;
+ break;
case SPRN_ICTC:
case SPRN_THRM1:
case SPRN_THRM2:
@@ -567,6 +576,15 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu,
int sprn, ulong *spr_val
case SPRN_EBBRR:
*spr_val = vcpu->arch.ebbrr;
break;
+ case SPRN_TFHAR:
+ *spr_val = vcpu->arch.tfhar;
+ break;
+ case SPRN_TEXASR:
+ *spr_val = vcpu->arch.texasr;
+ break;
+ case SPRN_TFIAR:
+ *spr_val = vcpu->arch.tfiar;
+ break;
case SPRN_THRM1:
case SPRN_THRM2:
case SPRN_THRM3:
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 9e22e7b..aeb87f6 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -785,7 +785,8 @@ static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong
fac)
{
BUG_ON(!cpu_has_feature(CPU_FTR_ARCH_207S));
- if (!(vcpu->arch.fscr & (1ULL << fac))) {
+ /* We get TM interrupts only when EBB is disabled? Sigh. */
+ if ((fac != FSCR_TM_LG) && !(vcpu->arch.fscr & (1ULL << fac))) {
/* Facility not enabled by the guest */
kvmppc_trigger_fac_interrupt(vcpu, fac);
return RESUME_GUEST;
--
1.8.1.4
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