On Tue, Jul 08, 2014 at 02:22:25PM +0000, Liang, Kan wrote: > > This too is wrong in many ways; there's more than 2 extra_msrs on many > > systems. > > > Right, there are four extra reg types on Intel systems. Since my > previous test only triggers the crash with RSP_0 and RSP_1, so I only > handle these two msrs. I will handle all the extra msrs then.
Yeah, so to other two are PEBS related, and I think we disable PEBS early on so you'll never hit them or something; didn't look too closely. > > And the place you check is abysmal, if we know at init time that we don't > > have those MSRs, WTF do you allow event creation that would use them, > > only to then misbehave? > > Right, we can check it at all the possible creation places. I think > the most common place to check should be x86_pmu_extra_regs. For > RSP_0 and RSP_1, I also plan to do the check in intel_fixup_er, so > extra_reg will not be updated. For LBR select, lbr_sel_map will be > cleared at runtime once check_msr failed. Besides the three places, > is there any place I missed? I think that's sufficient; but didn't stare too hard.
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