On 25 July 2014 15:02, Joel Schopp <joel.sch...@amd.com> wrote:
>> --- a/virt/kvm/arm/vgic.c
>> +++ b/virt/kvm/arm/vgic.c
>> @@ -1539,6 +1539,14 @@ int kvm_vgic_hyp_init(void)
>>                 goto out_unmap;
>>         }
>>
>> +       if (!PAGE_ALIGNED(resource_size(&vcpu_res))) {
>> +               kvm_err("GICV size 0x%llx not a multiple of page size 
>> 0x%lx\n",
>> +                       (unsigned long long)resource_size(&vcpu_res),
>> +                       PAGE_SIZE);
>> +               ret = -ENXIO;
>> +               goto out_unmap;
>> +       }
>> +
>>         vgic_vcpu_base = vcpu_res.start;
>>
>>         kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
> This would break with my SOC device tree which looks like this.  Note
> this device tree works just fine without checks.
>
>     gic: interrupt-controller@e1101000 {
>         compatible = "arm,gic-400-v2m";
>         #interrupt-cells = <3>;
>         #address-cells = <0>;
>         interrupt-controller;
>         msi-controller;
>         reg = <0x0 0xe1110000 0 0x1000>, /* gic dist */
>               <0x0 0xe112f000 0 0x2000>, /* gic cpu */
>               <0x0 0xe114f000 0 0x2000>, /* gic virtual ic*/
>               <0x0 0xe116f000 0 0x2000>, /* gic virtual cpu*/
>               <0x0 0xe1180000 0 0x1000>; /* gic msi */
>         interrupts = <1 8 0xf04>;
>     };

That has a non-aligned GICV -- does it really work on a
mainline kernel without Marc's patches to cope with GICV
which aren't at the base of a page? I can't see how...

thanks
-- PMM
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