On Sun, Sep 28 2014 at 03:04:26 PM, Christoffer Dall
<christoffer.d...@linaro.org> wrote:
> The EIRSR and ELRSR registers are 32-bit registers on GICv2, and we
> store these as an array of two such registers on the vgic vcpu struct.
> However, we access them as a single 64-bit value or as a bitmap pointer
> in the generic vgic code, which breaks BE support.
>
> Instead, store them as u64 values on the vgic structure and do the
> word-swapping in the assembly code, which already handles the byte order
> for BE systems.
>
> Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
(still going through my email backlog, hence the delay).
This looks like a valuable fix. Haven't had a chance to try it (no BE
setup at hand) but maybe Victor can help reproducing this?.
Acked-by: Marc Zyngier <marc.zyng...@arm.com>
M.
--
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