On 09/07/2015 04:30, Xiao Guangrong wrote:
>>>> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
>>>> index 602b974a60a6..0f125c1860ec 100644
>>>> --- a/arch/x86/kvm/svm.c
>>>> +++ b/arch/x86/kvm/svm.c
>>>> @@ -1085,6 +1085,47 @@ static u64 svm_compute_tsc_offset(struct
>>>> kvm_vcpu *vcpu, u64 target_tsc)
>>>> return target_tsc - tsc;
>>>> }
>>>>
>>>> +static void svm_set_guest_pat(struct vcpu_svm *svm, u64 *g_pat)
>>>> +{
>>>> + struct kvm_vcpu *vcpu = &svm->vcpu;
>>>> +
>>>> + /* Unlike Intel, AMD takes the guest's CR0.CD into account.
>>>
>>> I noticed this code in svm_set_cr0():
>>>
>>> if (!(vcpu->kvm->arch.disabled_quirks & KVM_QUIRK_CD_NW_CLEARED))
>>> cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
>>>
>>> gCR0.CD is hidden to CPU if KVM_QUIRK_CD_NW_CLEARED is not set and looks
>>> like it is the normal case after grepping Qemu code.
Hi Xiao,
yes, this is correct. QEMU still does not have support for disabling
"quirks", so gCR0.CD is currently hidden on SVM. I would like to
include this series in 4.2, while for 4.3 I will disable the quirk above
altogether (it is superseded by the way PAT is forced to all-WB).
In any case, this is just a KVM limitation. gCR0.CD is taken into
account by the processor when computing the effective memory type. It
uses all of these:
- the guest page tables PAT/PCD/PWT
- the guest page tables CR3.PCD/CR3.PWD
- the nested page tables PAT/PCD/PWT
- the guest page tables CR3.PCD/CR3.PWD
- the host MTRRs
- gCR0.CD
- hCR0.CD
Paolo
> How about this one? I still do not know how SVM properly emulates
> CR0.CD? :(
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