2015-11-24 01:26+0000, Wu, Feng: > "I don't think we do any vector hashing on our client parts. This may be why > the customer is not able to detect this on Skylake client silicon. > The vector hashing is micro-architectural and something we had done on server > parts. > > If you look at the haswell server CPU spec > (https://www-ssl.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf) > In section 4.1.2, you will see an IntControl register (this is a register > controlled/configured by BIOS) - see below.
Thank you! > If you look at bits 6:4 in that register, you see the option we offer in > hardware for what kind of redirection is applied to lowest priority > interrupts. > There are three options: > 1. Fixed priority > 2. Redirect last > 3. Hash Vector > > If picking vector hash, then bits 10:8 specifies the APIC-ID bits used for > the hashing." The hash function just interprets a subset of vector's bits as a number and uses that as a starting offset in a search for an enabled APIC within the destination set? For example: The x2APIC destination is 0x00000055 (= first four even APICs in cluster 0), the vector is 0b11100000, and bits 10:8 of IntControl are 000. 000 means that bits 7:4 of vector are selected, thus the vector hash is 0b1110 = 14, so the round-robin effectively does 14 % 4 (because we only have 4 destinations) and delivers to the 3rd possible APIC (= ID 6)? -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
