On Tue, 2009-05-12 at 23:41 +0100, Paul Brook wrote: > On Tuesday 12 May 2009, Alex Williamson wrote: > > Bit 0 is the enable bit, which we not only don't want to set, but > > it will stick and make us think it's an I/O port resource. > > Why is the ROM slot special? Doesn't the same apply to all BARs?
The PCI option (or expansion) ROM is assumed to be in MMIO space, so bit 0 becomes the enable bit rather than the memory space flag. The option ROM is also only a 4 byte register. The regular 6 base address registers can support MMIO or I/O port addresses and for PCI 2.0 (iirc), 2 regular base address registers can be combined to describe an 8 byte address. You can look at drivers/pci/probe.c:__pci_read_base() in the Linux source code and note that it makes the same special case for sizing the ROM BAR (~PCI_ROM_ADDRESS_ENABLE vs ~0). Alex -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
