On 02/25/10 18:34, Joerg Roedel wrote:
The biggest problem I see here is teaching the guest about the available events. The available event sets are dependent on the processor family (at least on AMD). A simple approach would be shadowing the perf msrs which is a simple thing to do. More problematic is the reinjection of performance interrupts and performance nmis.
IMHO the only real solution here is to map it to the host CPU, and require -cpu host for PMU support. There is no point in trying to emulate PMU features which we don't have in the hardware. Ie. you cannot count cache misses if the hardware doesn't support it. Cheers, Jes -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
