In the unlikely case that L1 does not capture MSR_IA32_TSC, L0 needs to
emulate this MSR write by L2 by modifying vmcs02.tsc_offset.
We also need to set vmcs12.tsc_offset, for this change to survive the next
nested entry (see prepare_vmcs02()).
Signed-off-by: Nadav Har'El <n...@il.ibm.com>
---
arch/x86/kvm/vmx.c | 11 +++++++++++
1 file changed, 11 insertions(+)
--- .before/arch/x86/kvm/vmx.c 2011-01-26 18:06:06.000000000 +0200
+++ .after/arch/x86/kvm/vmx.c 2011-01-26 18:06:06.000000000 +0200
@@ -1655,12 +1655,23 @@ static u64 guest_read_tsc(void)
static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
{
vmcs_write64(TSC_OFFSET, offset);
+ if (is_guest_mode(vcpu))
+ /*
+ * We are only changing TSC_OFFSET when L2 is running if for
+ * some reason L1 chose not to trap the TSC MSR. Since
+ * prepare_vmcs12() does not copy tsc_offset, we need to also
+ * set the vmcs12 field here.
+ */
+ get_vmcs12_fields(vcpu)->tsc_offset = offset -
+ to_vmx(vcpu)->nested.vmcs01_fields->tsc_offset;
}
static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
{
u64 offset = vmcs_read64(TSC_OFFSET);
vmcs_write64(TSC_OFFSET, offset + adjustment);
+ if (is_guest_mode(vcpu))
+ get_vmcs12_fields(vcpu)->tsc_offset += adjustment;
}
static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
--
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