On 07/25/2011 08:38 AM, Avi Kivity wrote:
On 07/25/2011 04:35 PM, Gleb Natapov wrote:
>
> That's the ISA TOM (15MB hole and friends).
>
Correct. What about:
3.2.19. DRB[0:7] DRAM ROW BOUNDARY REGISTERS
from 440fx spec?
Maybe. But we can't use that, since it ignores address line 31.
(440fx supports only 1GB RAM, and we're ignoring that)
What are we trying to do?
Can't we just register highest RAM address under 4G to 4G as PCI memory
and call it a day?
Do we really need a guest visible register to do this?
Regards,
Anthony Liguori
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